Tags: polarfire-soc/icicle-kit-reference-design
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Icicle Kit Reference Design Release v2023.06 Changes since last release - Add support for the Industrial Edge demo by adding two new GPIOS for the MikroBus connector - Change the datawidth used for the CoreAXI4DMAController in the AXI4Stream demo example to be 64'b from 32'b. This change allows the CoreAXI4DMAController to transfer data at a higher maximum rate - Resolve a bug with the AXI Stream data generator module which was incorrectly implementing the AXI4 Stream specification
Icicle Kit Reference Design Release v2023.02 Changes since last release: * Re-generate the MSS configuration file with the 2022.3 MSS configurator * Update MSS Configuration to overlay DDR memory locations - The 32 bit cached, 32 bit non-cached, 38 bit cached and 38 bit non-cached DDR now point to the same physical addresses (0x0) of DDR in the Linux configuration * Add a try error block around downloaded cores - if a core can't be downloaded, e.g. on a system with no internet access, the script will continue to run and only fail if a core isn't present in a vault. * Use latest version of CCC SG core in Vectorblox and DRI_CCC_DEMO argument designs * Add support for SMARTHLS argument design which allows the design and generation of a hardware module described in C++ using Microchip's SmartHLS tool - IMPORTANT: This flag is part of an Early Access Program for SmartHLS. If you are interested, please contact your local FAE or email us at SmartHLS@microchip.com for more details on how to enable this feature.
- Locked CCC used to generate fabric clocks to the NW PLL so the cloc…
…k frequency can be read by embedded software at run time
- Updated the FIC 3 clock frequency from 62.5MHz to 50MHz
- Memory map updates
- Updated the base addresses of FIC 0 peripherals
- Moved the PCIe to solely operate on in the FIC 1 domain
- Updated the base address of FIC 3 peripherals
- The memory map table in the readme should be consulted for the updated base addresses of all peripherals
- Wrapped components in SmartDesigns
- FIC 0 components are now contained in a "FIC_0_PERIPHERALS" SmartDesign
- FIC 1 components are now contained in a "FIC_1_PERIPHERALS" SmartDesign
- FIC 3 components are now contained in a "FIC_3_PERIPHERALS" SmartDesign
- FIC 3 address generation is contained in a "FIC_3_ADDRESS_GENERATION" SmartDesign
- Wrapped the MSS component in a SmartDesign to contain bibufs and additional components used to interface the MSS with the fabric
- Wrapped CoreI2C components in a SmartDesign to contain bibufs
- Updated all argument designs to support the latest base configuration
- Removed the AXI_ADDRESS_SHIM in the "BAREMETAL" argument configuration as this is expected to be a 32 bit configuration
- Added an additional CoreI2C to interface with the "ID_SC" and "ID_SD" pins of the RPi interface to read DT overlays from eeproms on RPi hats
- Renamed the "SDIO_register" to "fabric_sd_emmc_demux_select" to match the naming convention for embedded software
- Updated the HSS_UPDATE feature to use the new hex file naming convention in the HSS
- Updated the Tcl infrastructure to use wild cards for SgCores in the design - this should allow independence from Libero versions
- Removed the initial Libero version check in the base Tcl scripts
- Updated readme and block diagrams with the latest memory map configurations
- The "VECTORBLOX" argument design is now featured in the readme as a build target to add the VectorBlox CNN to the FPGA fabric
Added support for Libero 2022.1. Updated the core version for the PCI… …e block and the initialization monitor. The clock and reset generation structure has been updated to provide dedicated clocks for the fabric and FICs using the PolarFire SoC Clock Conditioning Circuitry (CCC). Added AXI4_STREAM_DEMO to demonstrate the AXI4 streaming capabilities of the AXI4 DMA controller and benchmark fabric to DDR performance
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