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ESP.getcyclecount() instruction in ISR causes fatal error: cache disabled but cached memory region accessed on ESP32 #113

@ianwillianb

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@ianwillianb

I found out that even though the ISR is store in IRAM, by default the instruction ESP.getcyclecount() is stored in flash, so if the access to flash is temporary disabled and an interrupt of type rxbitsISR() occurs the ESP32 ends up crashing.
I understand this is an issue out of the scope of the library, but this fact doesn't make it stable without adding IRAM_ATTR to the function ESP.getcyclecount() on ESP32.
Is there a way to change the way the ISR gets the number of cycles of the CPU, without compromising performance and functionality of the library?

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