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[CIRCT] Upgrade to 1.66.0
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@leonardt
leonardt committed Mar 11, 2024
1 parent f08e78c commit 6f48d04
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76 changes: 38 additions & 38 deletions examples/riscv_mini/tests/gold/test_riscv_mini_unflattened_tuples.v
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Original file line number Diff line number Diff line change
Expand Up @@ -3064,29 +3064,29 @@ module Control(
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
_GEN;
assign _GEN._0 = 2'h0;
assign _GEN._0 = 2'h3;
assign _GEN._1 = 1'h0;
assign _GEN._2 = 1'h0;
assign _GEN._3 = 3'h0;
assign _GEN._4 = 4'hF;
assign _GEN._5 = 3'h0;
assign _GEN._6 = 1'h0;
assign _GEN._6 = 1'h1;
assign _GEN._7 = 2'h0;
assign _GEN._8 = 3'h0;
assign _GEN._9 = 2'h0;
assign _GEN._9 = 2'h3;
assign _GEN._10 = 1'h0;
assign _GEN._11 = 3'h0;
assign _GEN._11 = 3'h4;
assign _GEN._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
_GEN_0;
assign _GEN_0._0 = 2'h3;
assign _GEN_0._0 = 2'h0;
assign _GEN_0._1 = 1'h0;
assign _GEN_0._2 = 1'h0;
assign _GEN_0._3 = 3'h0;
assign _GEN_0._4 = 4'hF;
assign _GEN_0._5 = 3'h0;
assign _GEN_0._6 = 1'h1;
assign _GEN_0._6 = 1'h0;
assign _GEN_0._7 = 2'h0;
assign _GEN_0._8 = 3'h0;
assign _GEN_0._9 = 2'h3;
Expand All @@ -3096,18 +3096,18 @@ module Control(
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
_GEN_1;
assign _GEN_1._0 = 2'h0;
assign _GEN_1._0 = 2'h2;
assign _GEN_1._1 = 1'h0;
assign _GEN_1._2 = 1'h0;
assign _GEN_1._3 = 3'h0;
assign _GEN_1._3 = 3'h6;
assign _GEN_1._4 = 4'hF;
assign _GEN_1._5 = 3'h0;
assign _GEN_1._6 = 1'h0;
assign _GEN_1._6 = 1'h1;
assign _GEN_1._7 = 2'h0;
assign _GEN_1._8 = 3'h0;
assign _GEN_1._9 = 2'h3;
assign _GEN_1._10 = 1'h0;
assign _GEN_1._11 = 3'h4;
assign _GEN_1._10 = 1'h1;
assign _GEN_1._11 = 3'h3;
assign _GEN_1._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
Expand All @@ -3123,7 +3123,7 @@ module Control(
assign _GEN_2._8 = 3'h0;
assign _GEN_2._9 = 2'h3;
assign _GEN_2._10 = 1'h1;
assign _GEN_2._11 = 3'h3;
assign _GEN_2._11 = 3'h2;
assign _GEN_2._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
Expand All @@ -3139,23 +3139,23 @@ module Control(
assign _GEN_3._8 = 3'h0;
assign _GEN_3._9 = 2'h3;
assign _GEN_3._10 = 1'h1;
assign _GEN_3._11 = 3'h2;
assign _GEN_3._11 = 3'h1;
assign _GEN_3._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
_GEN_4;
assign _GEN_4._0 = 2'h2;
assign _GEN_4._1 = 1'h0;
assign _GEN_4._1 = 1'h1;
assign _GEN_4._2 = 1'h0;
assign _GEN_4._3 = 3'h6;
assign _GEN_4._4 = 4'hF;
assign _GEN_4._3 = 3'h0;
assign _GEN_4._4 = 4'hA;
assign _GEN_4._5 = 3'h0;
assign _GEN_4._6 = 1'h1;
assign _GEN_4._7 = 2'h0;
assign _GEN_4._8 = 3'h0;
assign _GEN_4._9 = 2'h3;
assign _GEN_4._10 = 1'h1;
assign _GEN_4._11 = 3'h1;
assign _GEN_4._11 = 3'h3;
assign _GEN_4._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
Expand All @@ -3171,7 +3171,7 @@ module Control(
assign _GEN_5._8 = 3'h0;
assign _GEN_5._9 = 2'h3;
assign _GEN_5._10 = 1'h1;
assign _GEN_5._11 = 3'h3;
assign _GEN_5._11 = 3'h2;
assign _GEN_5._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
Expand All @@ -3187,34 +3187,34 @@ module Control(
assign _GEN_6._8 = 3'h0;
assign _GEN_6._9 = 2'h3;
assign _GEN_6._10 = 1'h1;
assign _GEN_6._11 = 3'h2;
assign _GEN_6._11 = 3'h1;
assign _GEN_6._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
_GEN_7;
assign _GEN_7._0 = 2'h2;
assign _GEN_7._1 = 1'h1;
assign _GEN_7._1 = 1'h0;
assign _GEN_7._2 = 1'h0;
assign _GEN_7._3 = 3'h0;
assign _GEN_7._4 = 4'hA;
assign _GEN_7._4 = 4'hF;
assign _GEN_7._5 = 3'h0;
assign _GEN_7._6 = 1'h1;
assign _GEN_7._7 = 2'h0;
assign _GEN_7._8 = 3'h0;
assign _GEN_7._9 = 2'h3;
assign _GEN_7._10 = 1'h1;
assign _GEN_7._11 = 3'h1;
assign _GEN_7._9 = 2'h0;
assign _GEN_7._10 = 1'h0;
assign _GEN_7._11 = 3'h0;
assign _GEN_7._12 = 1'h0;
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
_GEN_8;
assign _GEN_8._0 = 2'h2;
assign _GEN_8._0 = 2'h0;
assign _GEN_8._1 = 1'h0;
assign _GEN_8._2 = 1'h0;
assign _GEN_8._3 = 3'h0;
assign _GEN_8._4 = 4'hF;
assign _GEN_8._5 = 3'h0;
assign _GEN_8._6 = 1'h1;
assign _GEN_8._6 = 1'h0;
assign _GEN_8._7 = 2'h0;
assign _GEN_8._8 = 3'h0;
assign _GEN_8._9 = 2'h0;
Expand Down Expand Up @@ -3936,40 +3936,40 @@ module Control(
_GEN_81 = {{_GEN_9}, {_GEN_80[{inst[31:25], inst[14:12], inst[6:0]} == 17'h333]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_82 = {{_GEN}, {_GEN_81[{inst[31:25], inst[14:12], inst[6:0]} == 17'h3B3]}};
_GEN_82 = {{_GEN_8}, {_GEN_81[{inst[31:25], inst[14:12], inst[6:0]} == 17'h3B3]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_83 = {{_GEN_8}, {_GEN_82[{inst[31:28], inst[19:0]} == 24'hF]}};
_GEN_83 = {{_GEN_7}, {_GEN_82[{inst[31:28], inst[19:0]} == 24'hF]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_84 = {{_GEN_7}, {_GEN_83[inst == 32'h100F]}};
_GEN_84 = {{_GEN_6}, {_GEN_83[inst == 32'h100F]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_85 = {{_GEN_6}, {_GEN_84[{inst[14:12], inst[6:0]} == 10'hF3]}};
_GEN_85 = {{_GEN_5}, {_GEN_84[{inst[14:12], inst[6:0]} == 10'hF3]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_86 = {{_GEN_5}, {_GEN_85[{inst[14:12], inst[6:0]} == 10'h173]}};
_GEN_86 = {{_GEN_4}, {_GEN_85[{inst[14:12], inst[6:0]} == 10'h173]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_87 = {{_GEN_4}, {_GEN_86[{inst[14:12], inst[6:0]} == 10'h1F3]}};
_GEN_87 = {{_GEN_3}, {_GEN_86[{inst[14:12], inst[6:0]} == 10'h1F3]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_88 = {{_GEN_3}, {_GEN_87[{inst[14:12], inst[6:0]} == 10'h2F3]}};
_GEN_88 = {{_GEN_2}, {_GEN_87[{inst[14:12], inst[6:0]} == 10'h2F3]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_89 = {{_GEN_2}, {_GEN_88[{inst[14:12], inst[6:0]} == 10'h373]}};
_GEN_89 = {{_GEN_1}, {_GEN_88[{inst[14:12], inst[6:0]} == 10'h373]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_90 = {{_GEN_1}, {_GEN_89[{inst[14:12], inst[6:0]} == 10'h3F3]}};
_GEN_90 = {{_GEN_0}, {_GEN_89[{inst[14:12], inst[6:0]} == 10'h3F3]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_91 = {{_GEN_1}, {_GEN_90[inst == 32'h73]}};
_GEN_91 = {{_GEN_0}, {_GEN_90[inst == 32'h73]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_92 = {{_GEN_0}, {_GEN_91[inst == 32'h100073]}};
_GEN_92 = {{_GEN}, {_GEN_91[inst == 32'h100073]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }[1:0]
_GEN_93 = {{_GEN}, {_GEN_92[inst == 32'h10000073]}};
_GEN_93 = {{_GEN_8}, {_GEN_92[inst == 32'h10000073]}};
wire
struct packed {logic [1:0] _0; logic _1; logic _2; logic [2:0] _3; logic [3:0] _4; logic [2:0] _5; logic _6; logic [1:0] _7; logic [2:0] _8; logic [1:0] _9; logic _10; logic [2:0] _11; logic _12; }
_GEN_94 = _GEN_93[inst == 32'h10200073];
Expand Down
2 changes: 1 addition & 1 deletion setup.py
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@
"staticfg",
"networkx",
"uinspect",
"circt==1.59.1.dev51",
"circt==1.66.0",
],
python_requires='>=3.6',
long_description=long_description,
Expand Down
20 changes: 10 additions & 10 deletions tests/test_backend/test_mlir/golds/complex_lut.v
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Original file line number Diff line number Diff line change
Expand Up @@ -4,18 +4,18 @@ module LUT(
);

wire [3:0] _GEN = '{1'h1, 1'h1, 1'h0, 1'h0};
wire [3:0] _GEN_0 = '{1'h0, 1'h1, 1'h1, 1'h1};
wire [3:0] _GEN_1 = '{1'h0, 1'h1, 1'h1, 1'h0};
wire [3:0] _GEN_2 = '{1'h1, 1'h0, 1'h0, 1'h0};
wire [3:0] _GEN_3 = '{1'h0, 1'h1, 1'h0, 1'h1};
wire [3:0] _GEN_4 = '{1'h1, 1'h0, 1'h1, 1'h1};
wire [3:0] _GEN_5 = '{1'h1, 1'h1, 1'h1, 1'h0};
wire [3:0] _GEN_6 = '{1'h0, 1'h0, 1'h1, 1'h0};
wire [3:0] _GEN_0 = '{1'h0, 1'h1, 1'h0, 1'h1};
wire [3:0] _GEN_1 = '{1'h1, 1'h1, 1'h1, 1'h0};
wire [3:0] _GEN_2 = '{1'h0, 1'h1, 1'h1, 1'h0};
wire [3:0] _GEN_3 = '{1'h0, 1'h0, 1'h1, 1'h0};
wire [3:0] _GEN_4 = '{1'h1, 1'h0, 1'h0, 1'h0};
wire [3:0] _GEN_5 = '{1'h1, 1'h0, 1'h1, 1'h1};
wire [3:0] _GEN_6 = '{1'h0, 1'h1, 1'h1, 1'h1};
wire struct packed {logic [7:0] x; logic y; } _GEN_7 =
'{x: {1'h0, _GEN_1[I], _GEN_6[I], _GEN_2[I], 1'h1, _GEN_4[I], 1'h1, _GEN_0[I]},
y: _GEN_5[I]};
'{x: {1'h0, _GEN_2[I], _GEN_3[I], _GEN_4[I], 1'h1, _GEN_5[I], 1'h1, _GEN_6[I]},
y: _GEN_1[I]};
wire struct packed {logic [7:0] x; logic y; } _GEN_8 =
'{x: {_GEN_0[I], _GEN_1[I], 1'h0, _GEN_2[I], _GEN_3[I], 1'h0, _GEN_4[I], _GEN_0[I]},
'{x: {_GEN_6[I], _GEN_2[I], 1'h0, _GEN_4[I], _GEN_0[I], 1'h0, _GEN_5[I], _GEN_6[I]},
y: _GEN[I]};
assign O = {{_GEN_8}, {_GEN_7}};
endmodule
Expand Down

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