Support random traffic simulation

1. COMPUTE_TILE_TESTNODE.md

@@ -36,10 +36,10 @@ pip install .
 ```sh
 # Generate system verilog wrapper file using floogen.
 # Overwrite default path for [--outdir] and [--pkg-outdir]
-floogen -c floogen/examples/compute_tile_array.yml --outdir hw --pkg-outdir hw
-floogen -c floogen/examples/compute_tile_array_5x4.yml --outdir hw --pkg-outdir hw
-floogen -c floogen/examples/chiplet.yml --outdir hw --pkg-outdir hw
-# floogen -c ../../floogen/examples/chiplet.yml --outdir ../../hw --pkg-outdir ../../hw --tb-outdir ../../hw/tb --util-outdir ../../util
+# floogen -c floogen/examples/compute_tile_array.yml --outdir hw --pkg-outdir hw
+# floogen -c floogen/examples/compute_tile_array_5x4.yml --outdir hw --pkg-outdir hw
+# floogen -c floogen/examples/chiplet.yml --outdir hw --pkg-outdir hw
+floogen -c floogen/examples/chiplet_all_dma.yml --outdir hw --pkg-outdir hw
 ```
 
 After running the above command, all file used to run the simulation and synthesis of the network configuration that described in .yml file is ready in the path that bender is pointing to. The detail for each file that generated by floogen is described at table 1. in the next section.
@@ -53,18 +53,25 @@ make jobs TRAFFIC_TB=compute_tile_array TRAFFIC_TYPE=random
 
 'TRAFFIC_TB' must set to 'compute_tile_array' for working with compute tile array structure. 'TRAFFIC_TYPE' of the above command can be change from 'random' to other type to change the DMA behavior, which is described at table 2. in the next section.
 
-4. Running simulation in VCS. The simple standalone simulation of FlooNoC is used when `DMA_TESTNODE=TRUE` is declared. In this standalone test mode, snitch cluster will be replace with DMA simulation model, and there is no require for snitch cluster repo to be locate locally. In case select between running simulation in batch mode and GUI mode. Verdi is used for interactive debugging in GUI mode. 'TB_DUT' must set to the name of top level testbench, which can be difference in case of 'name' in .yml file is changing. 'JOB_NAME' must set to 'compute_tile_array' for working with compute tile array structure.
+4. Running simulation in VCS. In this standalone test mode, snitch cluster will be replace with DMA simulation model, and there is no require for snitch cluster repo to be locate locally. In case select between running simulation in batch mode and GUI mode. Verdi is used for interactive debugging in GUI mode. 'TB_DUT' must set to the name of top level testbench, which can be difference in case of 'name' in .yml file is changing. 'JOB_NAME' must set to 'compute_tile_array' for working with compute tile array structure.
 
 To run the simulation in batch mode :
 
 ```sh
+# Build simulation binary for batch mode
+make bin/floo_noc_batch.vcs TB_DUT=tb_floo_compute_tile_array
 # Running simulation in batch mode
-make run-vcs-batch TB_DUT=tb_floo_compute_tile_array JOB_NAME=compute_tile_array DMA_TESTNODE=TRUE
+make run-vcs-batch JOB_NAME=compute_tile_array
 ```
 
 To run the simulation in GUI mode :
 
 ```sh
+# Build simulation binary for GUI mode
+make bin/floo_noc_gui.vcs TB_DUT=tb_floo_compute_tile_array
+# Running simulation in GUI mode
+make run-vcs JOB_NAME=compute_tile_array
+
 # Running simulation in GUI mode
 make run-vcs TB_DUT=tb_floo_compute_tile_array JOB_NAME=compute_tile_array DMA_TESTNODE=TRUE
 ```

Bender.local

@@ -0,0 +1,6 @@
+# Copyright 2020 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+overrides:
+    axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }

Makefile

@@ -212,31 +212,43 @@ compile-vcs-batch: work-vcs/compile_vcs.sh
 compile-vcs: VLOGAN_ARGS+=-debug_access+all
 compile-vcs: compile-vcs-batch
 
-run-vcs: VCS_FLAGS+=-debug_access+all
-run-vcs: SIMV_FLAGS+=-gui=elite
 
-run-vcs-common:
-ifdef DMA_TESTNODE
-	$(VCS) $(VCS_FLAGS) $(TB_DUT)
-	./simv $(SIMV_FLAGS)
-else
-# Generate VCS simulation binary
+
+# run-vcs-common:
+# ifdef DMA_TESTNODE
+# 	$(VCS) $(VCS_FLAGS) $(TB_DUT)
+# 	./simv $(SIMV_FLAGS)
+# else
+# # Generate VCS simulation binary
+# 	mkdir -p bin
+# 	$(VCS) $(VCS_FLAGS) -o bin/snitch_cluster.vcs -cc cc -cpp g++ $(TB_DUT) \
+# 	$(SNITCH_PATH)/../../../hw/ip/test/src/rtl_lib.cc \
+# 	$(SNITCH_PATH)/../../../hw/ip/test/src/common_lib.cc \
+# 	$(SNITCH_PATH)/generated/bootdata.cc \
+#     -CFLAGS "-std=c++14 -I$(SNITCH_PATH)/ \
+# 	-I$(SNITCH_PATH)/test \
+# 	-I$(SNITCH_PATH)/work/include \
+# 	-I$(SNITCH_PATH)/../../../hw/ip/test/src" \
+# 	-LDFLAGS "-L$(SNITCH_PATH)/work/lib" -lfesvr
+# # Run VCS simulation binary
+# 	./bin/snitch_cluster.vcs $(SNITCH_PATH)/$(SNITCH_SW) $(SIMV_FLAGS)
+# endif
+
+bin/floo_noc_gui.vcs: VCS_FLAGS+=-debug_access+all
+bin/floo_noc_gui.vcs: compile-vcs
 	mkdir -p bin
-	$(VCS) $(VCS_FLAGS) -o bin/snitch_cluster.vcs -cc cc -cpp g++ $(TB_DUT) \
-	$(SNITCH_PATH)/../../../hw/ip/test/src/rtl_lib.cc \
-	$(SNITCH_PATH)/../../../hw/ip/test/src/common_lib.cc \
-	$(SNITCH_PATH)/generated/bootdata.cc \
-    -CFLAGS "-std=c++14 -I$(SNITCH_PATH)/ \
-	-I$(SNITCH_PATH)/test \
-	-I$(SNITCH_PATH)/work/include \
-	-I$(SNITCH_PATH)/../../../hw/ip/test/src" \
-	-LDFLAGS "-L$(SNITCH_PATH)/work/lib" -lfesvr
-# Run VCS simulation binary
-	./bin/snitch_cluster.vcs $(SNITCH_PATH)/$(SNITCH_SW) $(SIMV_FLAGS)
-endif
+	$(VCS) $(VCS_FLAGS) -o bin/floo_noc_gui.vcs $(TB_DUT)
+
+bin/floo_noc_batch.vcs: compile-vcs-batch
+	mkdir -p bin
+	$(VCS) $(VCS_FLAGS) -o bin/floo_noc_batch.vcs $(TB_DUT)
+
+run-vcs: SIMV_FLAGS+=-gui=elite
+run-vcs:
+	./bin/floo_noc_gui.vcs $(SIMV_FLAGS)
 
-run-vcs: compile-vcs run-vcs-common
-run-vcs-batch: compile-vcs-batch run-vcs-common
+run-vcs-batch:
+	./bin/floo_noc_batch.vcs $(SIMV_FLAGS)
 
 clean-vcs:
 	rm -rf work-vcs/compile_vcs.sh
@@ -256,6 +268,7 @@ clean-vcs:
 	rm -rf verdi_config_file
 	rm -rf verdiLog
 	rm -rf simv.vdb
+	rm -rf sysBusyPLog
 
 #############################################
 # Random testing for Compute tile structure #