Skip to content

Commit

Permalink
FlooNoC can run with all condition of IdWidthIn and IdWidthOut. Borde…
Browse files Browse the repository at this point in the history
…rId parameter can automatically generate by floogen. Still not be able to run random testing that need to update testbench code first.
  • Loading branch information
Attapon-Bunwong committed May 2, 2024
1 parent 2f3f6e9 commit 20bf6c6
Show file tree
Hide file tree
Showing 39 changed files with 5,011 additions and 1,786 deletions.
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,7 @@ novas.rc
simv.vdb
bin
logs
sysBusyPLog

# Fusion Compiler
fc_output.txt
Expand Down
3 changes: 3 additions & 0 deletions 1. COMPUTE_TILE_TESTNODE.md
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,9 @@ pip install .
# Generate system verilog wrapper file using floogen.
# Overwrite default path for [--outdir] and [--pkg-outdir]
floogen -c floogen/examples/compute_tile_array.yml --outdir hw --pkg-outdir hw
floogen -c floogen/examples/compute_tile_array_5x4.yml --outdir hw --pkg-outdir hw
# floogen -c floogen/examples/chiplet.yml --outdir hw --pkg-outdir hw
# floogen -c ../../floogen/examples/chiplet.yml --outdir ../../hw --pkg-outdir ../../hw --tb-outdir ../../hw/tb --util-outdir ../../util
```

After running the above command, all file used to run the simulation and synthesis of the network configuration that described in .yml file is ready in the path that bender is pointing to. The detail for each file that generated by floogen is described at table 1. in the next section.
Expand Down
File renamed without changes.
179 changes: 14 additions & 165 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@ packages:
dependencies:
- common_cells
axi:
revision: 49580dc3abce7ddfad70e4d8e719fe81a7a0667c
version: null
revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
version: 0.39.2
source:
Git: https://github.com/persimmonsai/axi.git
Git: https://github.com/pulp-platform/axi.git
dependencies:
- common_cells
- common_verification
Expand All @@ -25,193 +25,42 @@ packages:
- common_cells
- common_verification
common_cells:
revision: 33570c58014b4a9db098a2d37727000d6b3a6701
version: null
revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4
version: 1.35.0
source:
Git: https://github.com/persimmonsai/common_cells.git
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
- common_verification
- tech_cells_generic
common_verification:
revision: 9c07fa860593b2caabd9b5681740c25fac04b878
version: 0.2.3
source:
Git: https://github.com/persimmonsai/common_verification.git
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
fpnew:
revision: 1202ca3a767b563bca5de505574373e53941506f
version: null
source:
Git: https://github.com/openhwgroup/cvfpu.git
dependencies:
- common_cells
- fpu_div_sqrt_mvp
fpu_div_sqrt_mvp:
revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac
version: 1.0.4
source:
Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
dependencies:
- common_cells
future:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/future
dependencies:
- axi
- common_cells
idma:
revision: 7f02e225c8c4e9e60ad53e223e726574f36d9205
version: null
revision: ca1b28816a3706be0bf9ce01378246d5346384f0
version: 0.5.1
source:
Git: https://github.com/RomanPustobaiev/iDMA.git
Git: https://github.com/pulp-platform/iDMA.git
dependencies:
- axi
- common_cells
- common_verification
- register_interface
mem_interface:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/mem_interface
dependencies:
- common_cells
- reqrsp_interface
register_interface:
revision: 146501d80052b61475cdc333d3aab4cd769fd5dc
version: 0.3.9
source:
Git: https://github.com/persimmonsai/register_interface.git
Git: https://github.com/pulp-platform/register_interface.git
dependencies:
- apb
- axi
- common_cells
reqrsp_interface:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/reqrsp_interface
dependencies:
- axi
- common_cells
riscv-dbg:
revision: ec0d92fa5fdaaf611e5b8a4cc8ee84017ff98710
version: null
source:
Git: https://github.com/persimmonsai/riscv-dbg.git
dependencies:
- common_cells
- tech_cells_generic
snitch:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/snitch
dependencies:
- axi
- common_cells
- fpnew
- reqrsp_interface
- riscv-dbg
snitch_cluster:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster
dependencies:
- axi
- common_cells
- fpnew
- future
- mem_interface
- register_interface
- reqrsp_interface
- riscv-dbg
- snitch
- snitch_dma
- snitch_icache
- snitch_ipu
- snitch_ssr
- snitch_vm
- tcdm_interface
- tech_cells_generic
snitch_dma:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/snitch_dma
dependencies:
- axi
- common_cells
- snitch
snitch_icache:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/snitch_icache
dependencies:
- common_cells
- snitch
- tech_cells_generic
snitch_ipu:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/snitch_ipu
dependencies:
- common_cells
- snitch
snitch_ssr:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/snitch_ssr
dependencies:
- common_cells
- register_interface
- tcdm_interface
snitch_vm:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/snitch_vm
dependencies:
- common_cells
- snitch
system-snitch-cluster:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster
dependencies:
- axi
- snitch_cluster
- test
tcdm_interface:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/snitch_cluster/../../ip/tcdm_interface
dependencies:
- common_cells
- reqrsp_interface
tech_cells_generic:
revision: a9cae21902e75b1434328ecf36f85327ba5717de
version: 0.2.11
revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
version: 0.2.13
source:
Git: https://github.com/persimmonsai/tech_cells_generic.git
Git: https://github.com/pulp-platform/tech_cells_generic.git
dependencies:
- common_verification
test:
revision: null
version: null
source:
Path: ../PULP/snitch/hw/system/snitch_cluster/../../ip/test
dependencies:
- axi
- axi_riscv_atomics
- common_cells
- register_interface
- reqrsp_interface
79 changes: 64 additions & 15 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ dependencies:
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 }
#idma: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } # Temporary remove to not conflict with iDMA that declared inside snitch_cluster repos
idma: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
#system-snitch-cluster : {path: ../snitch/hw/system/snitch_cluster} # Temporary remove to be bender package for chiplet gen
#system-snitch-cluster : {path: ../PULP/snitch/hw/system/snitch_cluster}

Expand Down Expand Up @@ -43,43 +43,92 @@ sources:
- hw/floo_narrow_wide_chimney.sv
- hw/floo_router.sv
- hw/floo_narrow_wide_router.sv
#- hw/test/snitch_cluster_wrapper.sv # For Synthesis testing (exclude 'system-snitch-cluster')
# Level 3
#- hw/compute_tile.sv # Generated wrapper from floogen
#- hw/compute_tile_array_floo_noc.sv # Generated wrapper from floogen
#- hw/chiplet_floo_noc.sv # Generated wrapper from floogen for chiplet Top level

- target: test
include_dirs:
- hw/test
files:
# Level 0
- hw/floo_pkg.sv
- hw/floo_narrow_wide_pkg.sv
- hw/test/floo_test_pkg.sv
- hw/tb/compute_tile_array_test_pkg.sv
- hw/tb/chiplet_test_pkg.sv
# - hw/tb/compute_tile_array_test_pkg.sv
# - hw/tb/chiplet_test_pkg.sv
# Level 1
- hw/test/floo_axi_test_node.sv
- hw/test/floo_axi_rand_slave.sv
- hw/test/floo_dma_test_node.sv
- hw/test/axi_reorder_compare.sv
- hw/test/axi_reorder_remap_compare.sv
- hw/test/axi_bw_monitor.sv
- hw/test/floo_hbm_model.sv
- hw/test/snitch_cluster_test_node.sv
- hw/tb/floo_testharness.sv
# Level 2
- hw/test/floo_hbm_model.sv
# Level 3
- hw/tb/tb_floo_axi_chimney.sv
- hw/tb/tb_floo_narrow_wide_chimney.sv
- hw/tb/tb_floo_router.sv
- hw/tb/tb_floo_rob.sv
- hw/tb/tb_floo_dma_chimney.sv
- hw/tb/tb_floo_dma_nw_chimney.sv
- hw/tb/tb_floo_dma_mesh.sv

- target: dma_test
# dependencies:
# idma: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
files:
#- hw/test/snitch_cluster_wrapper.sv # For Synthesis testing (exclude 'system-snitch-cluster')
# Level 0
# - hw/floo_pkg.sv
# - hw/floo_narrow_wide_pkg.sv
# Level 1
- hw/compute_tile.sv # Generated wrapper from floogen
- hw/compute_tile_array_floo_noc.sv # Generated wrapper from floogen
- hw/chiplet_floo_noc.sv # Generated wrapper from floogen for chiplet Top level
# Level 0
# - hw/test/floo_test_pkg.sv
- hw/tb/compute_tile_array_test_pkg.sv
# Level 1
# - hw/test/floo_axi_test_node.sv
# - hw/test/floo_axi_rand_slave.sv
# - hw/test/floo_dma_test_node.sv
# - hw/test/axi_reorder_compare.sv
# - hw/test/axi_reorder_remap_compare.sv
# - hw/test/axi_bw_monitor.sv
# Level 2
# - hw/test/floo_hbm_model.sv
- hw/test/snitch_cluster_test_node.sv
# Level 3
- hw/tb/tb_floo_compute_tile_array.sv
- hw/tb/tb_floo_chiplet.sv
- hw/tb/tb_floo_bin.sv

# - target: test
# include_dirs:
# - hw/test
# files:
# # Level 0
# - hw/floo_pkg.sv
# - hw/floo_narrow_wide_pkg.sv
# - hw/test/floo_test_pkg.sv
# - hw/tb/compute_tile_array_test_pkg.sv
# - hw/tb/chiplet_test_pkg.sv
# # Level 1
# - hw/test/floo_axi_test_node.sv
# - hw/test/floo_axi_rand_slave.sv
# - hw/test/floo_dma_test_node.sv
# - hw/test/axi_reorder_compare.sv
# - hw/test/axi_reorder_remap_compare.sv
# - hw/test/axi_bw_monitor.sv
# - hw/test/floo_hbm_model.sv
# - hw/test/snitch_cluster_test_node.sv
# - hw/tb/floo_testharness.sv
# # Level 2
# - hw/tb/tb_floo_axi_chimney.sv
# - hw/tb/tb_floo_narrow_wide_chimney.sv
# - hw/tb/tb_floo_router.sv
# - hw/tb/tb_floo_rob.sv
# - hw/tb/tb_floo_dma_chimney.sv
# - hw/tb/tb_floo_dma_nw_chimney.sv
# - hw/tb/tb_floo_dma_mesh.sv
# - hw/tb/tb_floo_compute_tile_array.sv
# - hw/tb/tb_floo_chiplet.sv
# - hw/tb/tb_floo_bin.sv

- target: any(synthesis,spyglass)
files:
Expand Down
20 changes: 10 additions & 10 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ SNITCH_SW ?= sw/tests/build/fp32_computation_vector.elf

BENDER_FLAGS += -t rtl
BENDER_FLAGS += -t test
BENDER_FLAGS += -t dma_test # use for local simulation of FlooNoC system
#BENDER_FLAGS += -t simulation
#BENDER_FLAGS += -t cv64a6_imafdc_sv39

Expand Down Expand Up @@ -198,19 +199,18 @@ clean-vsim:

.PHONY: compile-vcs compile-vcs-batch run-vcs run-vcs-batch clean-vcs

scripts/compile_vcs.sh: Bender.yml
work-vcs/compile_vcs.sh: Bender.yml
mkdir -p work-vcs
mkdir -p scripts
echo 'set ROOT [file normalize [file dirname [info script]]/..]' > scripts/compile_vcs.sh
$(BENDER) script vcs --vlog-arg="$(VLOGAN_ARGS)" $(BENDER_FLAGS) | grep -v "set ROOT" >> scripts/compile_vcs.sh
chmod +x scripts/compile_vcs.sh
echo 'set ROOT [file normalize [file dirname [info script]]/..]' > work-vcs/compile_vcs.sh
$(BENDER) script vcs --vlog-arg="$(VLOGAN_ARGS)" $(BENDER_FLAGS) | grep -v "set ROOT" >> work-vcs/compile_vcs.sh
chmod +x work-vcs/compile_vcs.sh

compile-vcs: VLOGAN_ARGS+=-debug_access+all
compile-vcs: scripts/compile_vcs.sh
scripts/compile_vcs.sh
compile-vcs-batch: work-vcs/compile_vcs.sh
work-vcs/compile_vcs.sh > work-vcs/compile.log

compile-vcs-batch: scripts/compile_vcs.sh
scripts/compile_vcs.sh
compile-vcs: VLOGAN_ARGS+=-debug_access+all
compile-vcs: compile-vcs-batch

run-vcs: VCS_FLAGS+=-debug_access+all
run-vcs: SIMV_FLAGS+=-gui=elite
Expand Down Expand Up @@ -239,7 +239,7 @@ run-vcs: compile-vcs run-vcs-common
run-vcs-batch: compile-vcs-batch run-vcs-common

clean-vcs:
rm -rf scripts/compile_vcs.sh
rm -rf work-vcs/compile_vcs.sh
rm -rf bin
rm -rf work-vcs
rm -rf AN.DB
Expand Down
Loading

0 comments on commit 20bf6c6

Please sign in to comment.