drivers: add mising braces to single line if statements

Following zephyr's style guideline, all if statements, including single
line statements shall have braces.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

drivers/adc/adc_npcx.c

@@ -761,8 +761,9 @@ static int adc_npcx_init(const struct device *dev)
 
 	/* Configure the ADC clock */
 	prescaler = ceiling_fraction(data->input_clk, NPCX_ADC_CLK);
-	if (prescaler > 0x40)
+	if (prescaler > 0x40) {
 		prescaler = 0x40;
+	}
 
 	/* Set Core Clock Division Factor in order to obtain the ADC clock */
 	SET_FIELD(inst->ATCTL, NPCX_ATCTL_SCLKDIV_FIELD, prescaler - 1);

drivers/cache/cache_aspeed.c

@@ -139,8 +139,9 @@ int cache_data_all(int op)
 	syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
 
 	/* enter critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		key = irq_lock();
+	}
 
 	ctrl &= ~DCACHE_CLEAN;
 	syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
@@ -151,8 +152,9 @@ int cache_data_all(int op)
 	__DSB();
 
 	/* exit critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		irq_unlock(key);
+	}
 
 	return 0;
 }
@@ -171,8 +173,9 @@ int cache_data_range(void *addr, size_t size, int op)
 	}
 
 	/* enter critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		key = irq_lock();
+	}
 
 	n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);
 
@@ -184,8 +187,9 @@ int cache_data_range(void *addr, size_t size, int op)
 	__DSB();
 
 	/* exit critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		irq_unlock(key);
+	}
 
 	return 0;
 }
@@ -201,8 +205,9 @@ int cache_instr_all(int op)
 	syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
 
 	/* enter critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		key = irq_lock();
+	}
 
 	ctrl &= ~ICACHE_CLEAN;
 	syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
@@ -212,8 +217,9 @@ int cache_instr_all(int op)
 	__ISB();
 
 	/* exit critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		irq_unlock(key);
+	}
 
 	return 0;
 }
@@ -234,8 +240,9 @@ int cache_instr_range(void *addr, size_t size, int op)
 	n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);
 
 	/* enter critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		key = irq_lock();
+	}
 
 	for (i = 0; i < n; i++) {
 		syscon_write_reg(dev, CACHE_INVALID_REG, 0);
@@ -245,8 +252,9 @@ int cache_instr_range(void *addr, size_t size, int op)
 	__DSB();
 
 	/* exit critical section */
-	if (!k_is_in_isr())
+	if (!k_is_in_isr()) {
 		irq_unlock(key);
+	}
 
 	return 0;
 }

drivers/clock_control/clock_control_npcx.c

@@ -36,8 +36,9 @@ static inline int npcx_clock_control_on(const struct device *dev,
 	struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
 	const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;
 
-	if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT)
+	if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {
 		return -EINVAL;
+	}
 
 	/* Clear related PD (Power-Down) bit of module to turn on clock */
 	NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit));
@@ -51,8 +52,9 @@ static inline int npcx_clock_control_off(const struct device *dev,
 	struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
 	const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;
 
-	if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT)
+	if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {
 		return -EINVAL;
+	}
 
 	/* Set related PD (Power-Down) bit of module to turn off clock */
 	NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit);

drivers/dma/dma_iproc_pax_v1.c

@@ -824,8 +824,9 @@ static int dma_iproc_pax_do_xfer(const struct device *dev,
 	set_ring_active(pd, idx, true);
 
 	ret = wait_for_pkt_completion(dev, idx, pl_len + 1);
-	if (ret)
+	if (ret) {
 		goto err_ret;
+	}
 
 	ret = poll_on_write_sync(dev, ring);
 	k_mutex_lock(&ring->lock, K_FOREVER);

drivers/dma/dma_iproc_pax_v2.c

@@ -413,10 +413,11 @@ static inline void set_ring_active(struct dma_iproc_pax_data *pd,
 	uint32_t val;
 
 	val = sys_read32(RM_RING_REG(pd, idx, RING_CONTROL));
-	if (active)
+	if (active) {
 		val |= RING_CONTROL_ACTIVE;
-	else
+	} else {
 		val &= ~RING_CONTROL_ACTIVE;
+	}
 	sys_write32(val, RM_RING_REG(pd, idx, RING_CONTROL));
 }
 
@@ -443,9 +444,9 @@ static int init_ring(struct dma_iproc_pax_data *pd, enum ring_idx idx)
 	sys_write32(RING_CONTROL_FLUSH, RM_RING_REG(pd, idx,
 						    RING_CONTROL));
 	do {
-		if (sys_read32(RM_RING_REG(pd, idx, RING_FLUSH_DONE)) &
-		    RING_FLUSH_DONE_MASK)
+		if (sys_read32(RM_RING_REG(pd, idx, RING_FLUSH_DONE)) & RING_FLUSH_DONE_MASK) {
 			break;
+		}
 		k_busy_wait(1);
 	} while (--timeout);
 
@@ -968,8 +969,9 @@ static int dma_iproc_pax_process_dma_blocks(const struct device *dev,
 						config->channel_direction,
 						block_config,
 						&non_hdr_bd_count);
-		if (ret)
+		if (ret) {
 			goto err;
+		}
 		block_config = block_config->next_block;
 	}
 

drivers/espi/espi_npcx.c

@@ -228,10 +228,11 @@ static void espi_bus_cfg_update_isr(const struct device *dev)
 						NPCX_ESPI_HOST_CH_EN(chan));
 			evt.evt_details = BIT(chan);
 
-			if (evt.evt_data)
+			if (evt.evt_data) {
 				inst->ESPICFG |= BIT(chan);
-			else
+			} else {
 				inst->ESPICFG &= ~BIT(chan);
+			}
 
 			espi_send_callbacks(&data->callbacks, dev, evt);
 		}
@@ -569,10 +570,11 @@ static int espi_npcx_send_vwire(const struct device *dev,
 
 	/* Get wire field and set/clear wire bit */
 	val = GET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE);
-	if (level)
+	if (level) {
 		val |= bitmask;
-	else
+	} else {
 		val &= ~bitmask;
+	}
 
 	SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
 	LOG_DBG("Send VW: VWEVSM%d 0x%08X", reg_idx, inst->VWEVSM[reg_idx]);

drivers/espi/host_subs_npcx.c

@@ -809,10 +809,11 @@ int npcx_host_periph_write_request(enum lpc_peripheral_opcode op,
 			!IS_BIT_SET(inst_kbc->HICTRL, NPCX_HICTRL_OBFMIE)) {
 			return -ENOTSUP;
 		}
-		if (data)
+		if (data) {
 			LOG_INF("%s: op 0x%x data %x", __func__, op, *data);
-		else
+		} else {
 			LOG_INF("%s: op 0x%x only", __func__, op);
+		}
 
 		switch (op) {
 		case E8042_WRITE_KB_CHAR:
@@ -1010,8 +1011,9 @@ int npcx_host_init_subs_core_domain(const struct device *host_bus_dev,
 
 		ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
 				&host_sub_cfg.clks_list[i]);
-		if (ret < 0)
+		if (ret < 0) {
 			return ret;
+		}
 	}
 
 	/* Configure EC legacy configuration IO base address to 0x4E. */

drivers/ethernet/eth_w5500.c

@@ -347,12 +347,13 @@ static int w5500_set_config(const struct device *dev,
 	if (IS_ENABLED(CONFIG_NET_PROMISCUOUS_MODE) &&
 	    type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) {
 		if (config->promisc_mode) {
-			if (!(mode & BIT(mr)))
+			if (!(mode & BIT(mr))) {
 				return -EALREADY;
 			}
+		}
 
-			/* clear */
-			WRITE_BIT(mode, mr, 0);
+		/* clear */
+		WRITE_BIT(mode, mr, 0);
 	} else {
 		if (mode & BIT(mr)) {
 			return -EALREADY;

drivers/ethernet/phy/phy_mii.c

@@ -260,25 +260,29 @@ static int phy_mii_cfg_link(const struct device *dev,
 		return -EIO;
 	}
 
-	if (adv_speeds & LINK_FULL_10BASE_T)
+	if (adv_speeds & LINK_FULL_10BASE_T) {
 		anar_reg |= MII_ADVERTISE_10_FULL;
-	else
+	} else {
 		anar_reg &= ~MII_ADVERTISE_10_FULL;
+	}
 
-	if (adv_speeds & LINK_HALF_10BASE_T)
+	if (adv_speeds & LINK_HALF_10BASE_T) {
 		anar_reg |= MII_ADVERTISE_10_HALF;
-	else
+	} else {
 		anar_reg &= ~MII_ADVERTISE_10_HALF;
+	}
 
-	if (adv_speeds & LINK_FULL_100BASE_T)
+	if (adv_speeds & LINK_FULL_100BASE_T) {
 		anar_reg |= MII_ADVERTISE_100_FULL;
-	else
+	} else {
 		anar_reg &= ~MII_ADVERTISE_100_FULL;
+	}
 
-	if (adv_speeds & LINK_HALF_100BASE_T)
+	if (adv_speeds & LINK_HALF_100BASE_T) {
 		anar_reg |= MII_ADVERTISE_100_HALF;
-	else
+	} else {
 		anar_reg &= ~MII_ADVERTISE_100_HALF;
+	}
 
 	bmcr_reg |= MII_BMCR_AUTONEG_ENABLE;
 

drivers/ethernet/phy_xlnx_gem.c

@@ -50,8 +50,9 @@ static uint16_t phy_xlnx_gem_mdio_read(
 	 * current command.
 	 */
 	do {
-		if (poll_cnt++ > 0)
+		if (poll_cnt++ > 0) {
 			k_busy_wait(100);
+		}
 		reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
 	if (poll_cnt == 10) {
@@ -82,8 +83,9 @@ static uint16_t phy_xlnx_gem_mdio_read(
 	 */
 	poll_cnt = 0;
 	do {
-		if (poll_cnt++ > 0)
+		if (poll_cnt++ > 0) {
 			k_busy_wait(100);
+		}
 		reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
 	if (poll_cnt == 10) {
@@ -127,8 +129,9 @@ static void phy_xlnx_gem_mdio_write(
 	 * current command.
 	 */
 	do {
-		if (poll_cnt++ > 0)
+		if (poll_cnt++ > 0) {
 			k_busy_wait(100);
+		}
 		reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
 	if (poll_cnt == 10) {
@@ -161,8 +164,9 @@ static void phy_xlnx_gem_mdio_write(
 	 */
 	poll_cnt = 0;
 	do {
-		if (poll_cnt++ > 0)
+		if (poll_cnt++ > 0) {
 			k_busy_wait(100);
+		}
 		reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);
 	if (poll_cnt == 10) {

drivers/flash/flash_stm32wbx.c

@@ -114,8 +114,9 @@ static int write_dword(const struct device *dev, off_t offset, uint64_t val)
 		 * However, keeping that code make it compatible with both
 		 * mechanisms.
 		 */
-		while (LL_FLASH_IsActiveFlag_OperationSuspended())
+		while (LL_FLASH_IsActiveFlag_OperationSuspended()) {
 			;
+		}
 
 		/* Enter critical section */
 		key = irq_lock();
@@ -250,8 +251,9 @@ static int erase_page(const struct device *dev, uint32_t page)
 		 * However, keeping that code make it compatible with both
 		 * mechanisms.
 		 */
-		while (LL_FLASH_IsActiveFlag_OperationSuspended())
+		while (LL_FLASH_IsActiveFlag_OperationSuspended()) {
 			;
+		}
 
 		/* Enter critical section */
 		key = irq_lock();

drivers/gpio/gpio_ite_it8xxx2.c

@@ -370,10 +370,11 @@ static int gpio_ite_configure(const struct device *dev,
 	 * Select open drain first, so that we don't glitch the signal
 	 * when changing the line to an output.
 	 */
-	if (flags & GPIO_OPEN_DRAIN)
+	if (flags & GPIO_OPEN_DRAIN) {
 		*reg_gpotr |= mask;
-	else
+	} else {
 		*reg_gpotr &= ~mask;
+	}
 
 	/* 1.8V or 3.3V */
 	reg_1p8v = &IT8XXX2_GPIO_GCRX(
@@ -396,10 +397,11 @@ static int gpio_ite_configure(const struct device *dev,
 
 	/* If output, set level before changing type to an output. */
 	if (flags & GPIO_OUTPUT) {
-		if (flags & GPIO_OUTPUT_INIT_HIGH)
+		if (flags & GPIO_OUTPUT_INIT_HIGH) {
 			*reg_gpdr |= mask;
-		else if (flags & GPIO_OUTPUT_INIT_LOW)
+		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
 			*reg_gpdr &= ~mask;
+		}
 	}
 
 	/* Set input or output. */
@@ -537,15 +539,17 @@ static int gpio_ite_pin_interrupt_configure(const struct device *dev,
 		uint8_t wuc_mask = gpio_irqs[gpio_irq].wuc_mask;
 
 		/* Set both edges interrupt. */
-		if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH)
+		if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
 			*(wubemr(wuc_group)) |= wuc_mask;
-		else
+		} else {
 			*(wubemr(wuc_group)) &= ~wuc_mask;
+		}
 
-		if (trig & GPIO_INT_TRIG_LOW)
+		if (trig & GPIO_INT_TRIG_LOW) {
 			*(wuemr(wuc_group)) |= wuc_mask;
-		else
+		} else {
 			*(wuemr(wuc_group)) &= ~wuc_mask;
+		}
 		/*
 		 * Always write 1 to clear the WUC status register after
 		 * modifying edge mode selection register (WUBEMR and WUEMR).