Update README.md

Author: patel-soham

README.md

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 # Dynamic pattern detector using verilog
 A project to implement dynamic pattern detector using verilog in different ways.
+- Dynamic pattern detector with variable number of bits in implicit style fsm which supports APB protocol to configure pattern register value. 
+- Dynamic 3 bit pattern detector in explicit style fsm.
+- Dynamic pattern detector with variable number of bits in implicit style fsm.
+
+---
+**Files**
+1. Implicit fsm with APB [design](!!!) and [testbench](!!!)
+2. Explicit fsm [design](dynamic_pattern_exp.v) and [testbench](tb_dynamic_pattern_exp.v)
+3. Implicit fsm [design](dynamic_pattern_imp.v) and [testbench](tb_dynamic_pattern_imp.v)