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Nov 26, 2024
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2 changes: 1 addition & 1 deletion models_internal/verilog/tb/DLY_SEL_DECODER_tb.v
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ module DLY_SEL_DECODER_tb;

integer error=0;

DLY_SEL_DCODER DLY_SEL_DCODER_inst (
DLY_SEL_DECODER DLY_SEL_DECODER_inst (
.DLY_LOAD(DLY_LOAD),
.DLY_ADJ(DLY_ADJ),
.DLY_INCDEC(DLY_INCDEC),
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