Skip to content

removing dma design #60

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 5, 2024
Merged

removing dma design #60

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 0 additions & 13 deletions models_internal/verilog/SOC_FPGA_INTF_DMA.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,18 +14,5 @@ module SOC_FPGA_INTF_DMA (
input DMA_RST_N // DMA reset
);


reg [3:0] dma_ack;
assign DMA_ACK = dma_ack;

always@(posedge DMA_CLK) begin
if(!DMA_RST_N) begin
dma_ack <= 4'b0;
end
else begin
dma_ack <= DMA_REQ;
end
end

endmodule
`endcelldefine
13 changes: 0 additions & 13 deletions models_internal/verilog/inc/SOC_FPGA_INTF_DMA.inc.v
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,13 +0,0 @@


reg [3:0] dma_ack;
assign DMA_ACK = dma_ack;

always@(posedge DMA_CLK) begin
if(!DMA_RST_N) begin
dma_ack <= 4'b0;
end
else begin
dma_ack <= DMA_REQ;
end
end