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Merged
merged 2 commits into from
Aug 13, 2024
Merged

Adding macro for specify blocks #54

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8c103e2
adding ifndef synthesis macro to specify blocks
muhammadhamza15 Aug 13, 2024
ff9923c
Merge pull request #24 from muhammadhamza15/mhamza_dev
muhammadhamza15 Aug 13, 2024
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19 changes: 10 additions & 9 deletions models_internal/verilog/CARRY.v
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Original file line number Diff line number Diff line change
Expand Up @@ -17,17 +17,18 @@ module CARRY (

assign {COUT, O} = {P ? CIN : G, P ^ CIN};

specify

if (P == 1'b1)
(CIN => COUT) = (0, 0);
if (P == 1'b0)
(G => COUT) = (0, 0);
`ifndef SYNTHESIS
specify

( P, CIN *> O ) = (0, 0);
if (P == 1'b1)
(CIN => COUT) = (0, 0);
if (P == 1'b0)
(G => COUT) = (0, 0);

endspecify
( P, CIN *> O ) = (0, 0);

endspecify
`endif // `ifndef SYNTHESIS


endmodule
`endcelldefine
9 changes: 6 additions & 3 deletions models_internal/verilog/CLK_BUF.v
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Expand Up @@ -14,9 +14,12 @@ module CLK_BUF (

assign O = I ;

specify
(I => O) = (0, 0);
endspecify
`ifndef SYNTHESIS
specify
(I => O) = (0, 0);
endspecify
`endif // `ifndef SYNTHESIS



endmodule
Expand Down
97 changes: 50 additions & 47 deletions models_internal/verilog/DFFNRE.v
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Expand Up @@ -22,57 +22,60 @@ module DFFNRE (
else if (E)
Q <= D;

wire C_D_SDFCHK;
wire C_nD_SDFCHK;
wire nC_D_SDFCHK;
wire nC_nD_SDFCHK;
wire R_D_SDFCHK;
wire R_nD_SDFCHK;
wire R_SDFCHK;
wire D_SDFCHK;
`ifndef SYNTHESIS
wire C_D_SDFCHK;
wire C_nD_SDFCHK;
wire nC_D_SDFCHK;
wire nC_nD_SDFCHK;
wire R_D_SDFCHK;
wire R_nD_SDFCHK;
wire R_SDFCHK;
wire D_SDFCHK;

assign C_D_SDFCHK = C & D;
assign C_nD_SDFCHK = C & !D;
assign nC_D_SDFCHK = !C & D;
assign nC_nD_SDFCHK = !C & !D;
assign R_D_SDFCHK = R & D;
assign R_nD_SDFCHK = R & !D;
assign R_SDFCHK = R;
assign D_SDFCHK = D;
assign C_D_SDFCHK = C & D;
assign C_nD_SDFCHK = C & !D;
assign nC_D_SDFCHK = !C & D;
assign nC_nD_SDFCHK = !C & !D;
assign R_D_SDFCHK = R & D;
assign R_nD_SDFCHK = R & !D;
assign R_SDFCHK = R;
assign D_SDFCHK = D;


specify
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
(negedge C => (Q+:D)) = (0, 0);
specify
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
(negedge C => (Q+:D)) = (0, 0);

$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);

$setuphold (negedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
$setuphold (negedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
$recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier);
$hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier);
endspecify
`endif // `ifndef SYNTHESIS

$setuphold (negedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
$setuphold (negedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
$recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier);
$hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier);
endspecify
endmodule
`endcelldefine
99 changes: 51 additions & 48 deletions models_internal/verilog/DFFRE.v
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Expand Up @@ -22,58 +22,61 @@ module DFFRE (
else if (E)
Q <= D;

wire C_D_SDFCHK;
wire C_nD_SDFCHK;
wire nC_D_SDFCHK;
wire nC_nD_SDFCHK;
wire R_D_SDFCHK;
wire R_nD_SDFCHK;
wire R_SDFCHK;
wire D_SDFCHK;
`ifndef SYNTHESIS
wire C_D_SDFCHK;
wire C_nD_SDFCHK;
wire nC_D_SDFCHK;
wire nC_nD_SDFCHK;
wire R_D_SDFCHK;
wire R_nD_SDFCHK;
wire R_SDFCHK;
wire D_SDFCHK;

assign C_D_SDFCHK = C & D;
assign C_nD_SDFCHK = C & !D;
assign nC_D_SDFCHK = !C & D;
assign nC_nD_SDFCHK = !C & !D;
assign R_D_SDFCHK = R & D;
assign R_nD_SDFCHK = R & !D;
assign R_SDFCHK = R;
assign D_SDFCHK = D;
assign C_D_SDFCHK = C & D;
assign C_nD_SDFCHK = C & !D;
assign nC_D_SDFCHK = !C & D;
assign nC_nD_SDFCHK = !C & !D;
assign R_D_SDFCHK = R & D;
assign R_nD_SDFCHK = R & !D;
assign R_SDFCHK = R;
assign D_SDFCHK = D;


specify
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
(posedge C => (Q+:D)) = (0, 0);
specify
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
(negedge R => (Q+:1'b0)) = (0, 0);
(posedge C => (Q+:D)) = (0, 0);

$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);

$setuphold (posedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
$setuphold (posedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
$recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier);
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
endspecify
$setuphold (posedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
$setuphold (posedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
$recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier);
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
endspecify
`endif // `ifndef SYNTHESIS

endmodule
`endcelldefine
8 changes: 5 additions & 3 deletions models_internal/verilog/FCLK_BUF.v
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Expand Up @@ -14,9 +14,11 @@ module FCLK_BUF (

assign O = I ;

specify
(I => O) = (0, 0);
endspecify
`ifndef SYNTHESIS
specify
(I => O) = (0, 0);
endspecify
`endif // `ifndef SYNTHESIS


endmodule
Expand Down
11 changes: 7 additions & 4 deletions models_internal/verilog/I_BUF.v
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Expand Up @@ -25,10 +25,13 @@ module I_BUF #(

assign O = EN ? I : 1'b0;

specify
if (EN == 1'b1)
(I => O) = (0, 0);
endspecify
`ifndef SYNTHESIS
specify
if (EN == 1'b1)
(I => O) = (0, 0);
endspecify
`endif // `ifndef SYNTHESIS

initial begin
case(WEAK_KEEPER)
"NONE" ,
Expand Down
10 changes: 6 additions & 4 deletions models_internal/verilog/I_BUF_DS.v
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Expand Up @@ -37,10 +37,12 @@ module I_BUF_DS #(
endcase
end

specify
if (EN == 1'b1)
( I_P, I_N *> O ) = (0, 0);
endspecify
`ifndef SYNTHESIS
specify
if (EN == 1'b1)
( I_P, I_N *> O ) = (0, 0);
endspecify
`endif // `ifndef SYNTHESIS

initial begin
case(WEAK_KEEPER)
Expand Down
9 changes: 6 additions & 3 deletions models_internal/verilog/O_BUF.v
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Expand Up @@ -20,9 +20,12 @@ module O_BUF

assign O = I ;

specify
(I => O) = (0, 0);
endspecify initial begin
`ifndef SYNTHESIS
specify
(I => O) = (0, 0);
endspecify
`endif // `ifndef SYNTHESIS
initial begin

case(IOSTANDARD)
"DEFAULT" ,
Expand Down
11 changes: 7 additions & 4 deletions models_internal/verilog/O_BUF_DS.v
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Expand Up @@ -21,10 +21,13 @@ module O_BUF_DS
assign O_P = I;
assign O_N = ~I;

specify
(I => O_P) = (0, 0);
(I => O_N) = (0, 0);
endspecify
`ifndef SYNTHESIS
specify
(I => O_P) = (0, 0);
(I => O_N) = (0, 0);
endspecify
`endif // `ifndef SYNTHESIS


initial begin

Expand Down
18 changes: 9 additions & 9 deletions models_internal/verilog/inc/CARRY.inc.v
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Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@

assign {COUT, O} = {P ? CIN : G, P ^ CIN};

specify

if (P == 1'b1)
(CIN => COUT) = (0, 0);
if (P == 1'b0)
(G => COUT) = (0, 0);
`ifndef SYNTHESIS
specify

( P, CIN *> O ) = (0, 0);
if (P == 1'b1)
(CIN => COUT) = (0, 0);
if (P == 1'b0)
(G => COUT) = (0, 0);

endspecify
( P, CIN *> O ) = (0, 0);


endspecify
`endif // `ifndef SYNTHESIS
9 changes: 6 additions & 3 deletions models_internal/verilog/inc/CLK_BUF.inc.v
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Original file line number Diff line number Diff line change
@@ -1,8 +1,11 @@

assign O = I ;

specify
(I => O) = (0, 0);
endspecify
`ifndef SYNTHESIS
specify
(I => O) = (0, 0);
endspecify
`endif // `ifndef SYNTHESIS



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