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Merged
merged 4 commits into from
Jun 28, 2024
Merged

Simulation Models Updates #39

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9f90323
Updated PLL model and tb (EDA-2855)
muhammadhamza15 Jun 27, 2024
817ea6d
modified OSERDES, Changed the LOAD_WORD signal to DATA_VALID
muhammadhamza15 Jun 27, 2024
346c41e
changed RX_RST signal name to RST in ISERDES
muhammadhamza15 Jun 28, 2024
348ab1d
Merge pull request #18 from muhammadhamza15/mhamza_dev
muhammadhamza15 Jun 28, 2024
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58 changes: 29 additions & 29 deletions models_customer/verilog/I_SERDES.v
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Original file line number Diff line number Diff line change
Expand Up @@ -250,7 +250,7 @@ module I_SERDES #(
parameter DPA_MODE = "NONE" // Select Dynamic Phase Alignment or Clock Data Recovery (NONE/DPA/CDR)
) (
input D, // Data input (connect to input port, buffer or I_DELAY)
input RX_RST, // Active-low asycnhronous reset
input RST, // Active-low asycnhronous reset
input BITSLIP_ADJ, // BITSLIP_ADJ input
input EN, // EN input data (input data is low when driven low)
input CLK_IN, // Fabric clock input
Expand Down Expand Up @@ -380,9 +380,9 @@ end
// DPA BLOCK //

// clk 0 check
always@(posedge clk_0 or negedge RX_RST)
always@(posedge clk_0 or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
clk0_data_reg<=0;
clk0_data_comp<=0;
Expand All @@ -409,9 +409,9 @@ begin
end

// clk 90 check
always@(posedge clk_90 or negedge RX_RST)
always@(posedge clk_90 or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
clk90_data_reg<=0;
clk90_data_comp<=0;
Expand All @@ -438,9 +438,9 @@ begin
end

// clk 180 check
always@(posedge clk_180 or negedge RX_RST)
always@(posedge clk_180 or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
clk180_data_reg<=0;
clk180_data_comp<=0;
Expand All @@ -467,9 +467,9 @@ begin
end

// clk 270 check
always@(posedge clk_270 or negedge RX_RST)
always@(posedge clk_270 or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
clk270_data_reg<=0;
clk270_data_comp<=0;
Expand Down Expand Up @@ -538,9 +538,9 @@ assign DPA_ERROR= dpa_error;

// FOR FAST CLOCK
// count cycles after PLL LOCK
always@(posedge PLL_CLK or negedge RX_RST)
always@(posedge PLL_CLK or negedge RST)
begin
if(!RX_RST)
if(!RST)
pll_lock_count<=0;
else if(!PLL_LOCK)
pll_lock_count<=0;
Expand All @@ -551,9 +551,9 @@ else if(PLL_LOCK && pll_lock_count<=255)
end

// Generate Core CLK And Word Load Enable
always@(posedge PLL_CLK or negedge RX_RST)
always@(posedge PLL_CLK or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
core_clk<=0;
core_clk_count<=0;
Expand All @@ -577,9 +577,9 @@ end
// FOR CDR CLOCK

// count cycles after PLL LOCK
always@(posedge cdr_clk or negedge RX_RST)
always@(posedge cdr_clk or negedge RST)
begin
if(!RX_RST)
if(!RST)
cdr_pll_lock_count<=0;
else if(!PLL_LOCK)
cdr_pll_lock_count<=0;
Expand All @@ -589,9 +589,9 @@ else if(PLL_LOCK && cdr_pll_lock_count<=255)
end

// Generate CDR Core CLK And Word Load Enable
always@(posedge cdr_clk or negedge RX_RST)
always@(posedge cdr_clk or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
cdr_core_clk<=0;
cdr_core_clk_count<=0;
Expand Down Expand Up @@ -626,12 +626,12 @@ afifo # (
)
afifo_dpa (
.wclk(cdr_clk),
.wr_reset(!RX_RST),
.wr_reset(!RST),
.wr(!dpa_fifo_full),
.wr_data(dpa_dout),
.wr_full(dpa_fifo_full),
.rclk(PLL_CLK),
.rd_reset(!RX_RST),
.rd_reset(!RST),
.rd(!dpa_fifo_empty),
.rd_data(dpa_fifo_dout),
.rd_empty(dpa_fifo_empty)
Expand All @@ -658,9 +658,9 @@ end
assign bitslip_adj_pulse = (bitslip_adj_1) && (!bitslip_adj_0);

// bitslip counter
always @(posedge bitslip_des_clk or negedge RX_RST)
always @(posedge bitslip_des_clk or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
bitslip_counter<=0;
bitslip_shifter_out<=0;
Expand All @@ -679,9 +679,9 @@ end
end

// bit shifter
always @(posedge bitslip_des_clk or negedge RX_RST)
always @(posedge bitslip_des_clk or negedge RST)
begin
if(!RX_RST)
if(!RST)
bit_shifter<=0;
else
bit_shifter<={bit_shifter[WIDTH-2:0],bitslip_din};
Expand All @@ -703,9 +703,9 @@ case(bitslip_counter)
endcase
end

always @(posedge bitslip_des_clk or negedge RX_RST)
always @(posedge bitslip_des_clk or negedge RST)
begin
if(!RX_RST)
if(!RST)
bitslip_dout<=0;
else
bitslip_dout<=bitslip_shifter_out;
Expand All @@ -715,9 +715,9 @@ end
// DE-SERIALIZER //

// SHIFTER+PARALLEL-REGISTER
always@(posedge bitslip_des_clk or negedge RX_RST)
always@(posedge bitslip_des_clk or negedge RST)
begin
if(!RX_RST)
if(!RST)
begin
des_shifter<=0;
des_parallel_reg<=0;
Expand All @@ -738,12 +738,12 @@ afifo # (
)
afifo_inst (
.wclk(bitslip_des_clk),
.wr_reset(!RX_RST),
.wr_reset(!RST),
.wr(!des_fifo_full && des_word_load_en),
.wr_data(des_parallel_reg),
.wr_full(des_fifo_full),
.rclk(CLK_IN),
.rd_reset(!RX_RST),
.rd_reset(!RST),
.rd(!des_fifo_empty),
.rd_data(Q),
.rd_empty(des_fifo_empty)
Expand Down
5 changes: 2 additions & 3 deletions models_customer/verilog/O_SERDES.v
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Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ module O_SERDES #(
) (
input [WIDTH-1:0] D, // D input bus
input RST, // Active-low, asynchronous reset
input LOAD_WORD, // Load word input
input DATA_VALID, // Active high data valid signal
input CLK_IN, // Fabric clock input
input OE_IN, // Output tri-state enable input
output OE_OUT, // Output tri-state enable output (conttect to O_BUFT or inferred tri-state signal)
Expand All @@ -81,7 +81,6 @@ module O_SERDES #(
);



// GBOX CLK GEN
reg core_clk=0;
reg word_load_en;
Expand Down Expand Up @@ -194,7 +193,7 @@ module O_SERDES #(
fifo_read_en <= 1'b1;
end

assign word_load_en_sync = LOAD_WORD && fifo_read_en ;
assign word_load_en_sync = DATA_VALID && fifo_read_en && word_load_en ;


// Parallel data register
Expand Down
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