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Commit 830bf91

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orhoskoorhosko
committed
Small refactor
1 parent a444163 commit 830bf91

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2 files changed

+126
-70
lines changed

2 files changed

+126
-70
lines changed

‎src/core/Core.sv

Lines changed: 51 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,7 @@ module Core (
7878
logic [31:0] program_counter = 32'h80000000;
7979

8080
logic [31:0] instruction;
81+
8182
logic [ 4:0] RF_rsel1;
8283
logic [ 4:0] RF_rsel2;
8384
logic [ 4:0] RF_wsel;
@@ -152,7 +153,7 @@ module Core (
152153

153154
logic [31:0] DM_OUT;
154155
DataMem dm (
155-
.rclk(clk), //sig_data_read),
156+
.rclk(clk), //sig_data_read),
156157
.wclk(clk),
157158
.data_in(RF_rdata2),
158159
.addr_in(mmu_addr_out),
@@ -190,26 +191,12 @@ module Core (
190191

191192
logic [31:0] MMU_OUT;
192193
always_ff @(negedge clk) begin
193-
if (sig_compute) begin //TODO: sadasdasd
194-
MMU_OUT <= (mem_sel == `MEM_SEL_SRAM) ? DM_OUT :
194+
if (sig_compute) begin //TODO: sadasdasd
195+
MMU_OUT <= (mem_sel == `MEM_SEL_SRAM) ? DM_OUT :
195196
(mem_sel == `MEM_SEL_UART) ? {24'h000000, UART_OUT} :
196197
(mem_sel == `MEM_SEL_I2C) ? 32'h00000000 : //? {24'h000000, I2C_OUT} :
197-
32'h00000078;
198+
32'h00000078;
198199
end
199-
200-
/*
201-
if (mem_sel == 2'b11 && RF_wdata_sel == `RF_WDATA_SEL_DM && RF_wen)
202-
$display(
203-
"WHY THE FUCK YOU ARE HERE, mem_sel=%b, %b %b %b %b, %h",
204-
mem_sel,
205-
sig_read_im,
206-
sig_data_read,
207-
sig_compute,
208-
sig_write_back,
209-
ALU_OUT
210-
);
211-
*/
212-
213200
end
214201

215202
logic [31:0] ALU_A;
@@ -233,20 +220,8 @@ module Core (
233220
);
234221

235222
always_ff @(negedge clk) begin
236-
237-
//$display("pc: %h, alu: %h", program_counter, ALU_OUT);
238-
if(program_counter == 32'h80000100) begin
239-
240-
/*
241-
for(int i=0; i<640; i=i+1) begin
242-
$display("mem: %h", dm.mem[32'h960+i]);
243-
end
244-
*/
245-
246-
end
247-
248-
if(sig_write_back) begin
249-
// if (halt_sig) begin
223+
if (sig_write_back) begin
224+
// if (halt_sig) begin
250225
casez (instruction[6:0])
251226
B_TYPE: begin
252227
if (branch_taken == `BRANCH_SEL_ALU) begin
@@ -270,58 +245,64 @@ module Core (
270245
.imm(Immediate_imm)
271246
);
272247

273-
// reg halt_sig = 1;
248+
// reg halt_sig = 1;
274249

275250
assign leds[5] = btn;
276251
assign leds[4] = sig_write_back;
277252
assign leds[3] = uart.tx_data_ready;
278253
assign leds[2:0] = uart.uart_tx_inst.state[2:0];
279254

280-
/*
281-
assign leds[5:0] = program_counter[7:2];
282-
*/
283-
284-
`ifdef synth
255+
// ----------------------------------------------------
285256

286-
logic [31:0] gp;
287-
logic [31:0] tx_word;
288-
assign gp[31:0] = rf.registers[3];
289-
290-
function [7:0] hex_to_ascii;
291-
input [3:0] hex_digit_1;
292-
begin
293-
if ({4'b0, hex_digit_1} < 8'd10) hex_to_ascii = "0" + {4'b0, hex_digit_1};
294-
else hex_to_ascii = "A" + ({4'b0, hex_digit_1} - 8'd10);
257+
always_ff @(posedge clk) begin
258+
if (1) begin // TODO: add hazard detection
259+
pr_if_dr.instruction <= instruction;
260+
pr_if_dr.program_counter <= program_counter;
295261
end
296-
endfunction
262+
end
297263

298-
logic [31:0] pass[1];
299-
logic [31:0] fail[1];
264+
always_ff @(posedge clk) begin
265+
if (1) begin // TODO: add hazard detection
266+
pr_id_ex.RF_rdata1 <= RF_rdata1;
267+
pr_id_ex.RF_rdata2 <= RF_rdata2;
268+
pr_id_ex.Immediate_imm <= Immediate_imm;
269+
pr_id_ex.program_counter <= pr_if_dr.program_counter;
270+
271+
pr_id_ex.RF_rsel1 <= RF_rsel1;
272+
pr_id_ex.RF_rsel2 <= RF_rsel2;
273+
pr_id_ex.RF_wsel <= RF_wsel;
274+
pr_id_ex.RF_wen <= RF_wen;
275+
pr_id_ex.branch_taken <= branch_taken;
276+
pr_id_ex.DM_wen <= DM_wen;
277+
pr_id_ex.RF_wdata_sel <= RF_wdata_sel;
278+
pr_id_ex.mem_sel <= mem_sel;
279+
pr_id_ex.ALU_OP1_SEL <= ALU_OP1_SEL;
280+
pr_id_ex.ALU_OP2_SEL <= ALU_OP2_SEL;
281+
pr_id_ex.ALU_Operation <= ALU_Operation;
282+
pr_id_ex.branch_condition <= branch_condition;
283+
end
284+
end
300285

301-
initial begin
302-
//$readmemh("../../mem_files/rv32ui-p-tests/rv32ui-p-sw_pass.txt", pass);
303-
//$readmemh("../../mem_files/rv32ui-p-tests/rv32ui-p-sw_fail.txt", fail);
304-
leds[5:1] = 5'b00000;
286+
always_ff @(posedge clk) begin
287+
if (1) begin // TODO: add hazard detection
288+
pr_ex_mem.ALU_OUT <= ALU_OUT;
289+
pr_ex_mem.RF_wsel <= pr_id_ex.RF_wsel;
290+
pr_ex_mem.RF_wen <= pr_id_ex.RF_wen;
291+
pr_ex_mem.RF_wdata_sel <= pr_id_ex.RF_wdata_sel;
292+
pr_ex_mem.mem_sel <= pr_id_ex.mem_sel;
293+
pr_ex_mem.DM_wen <= pr_id_ex.DM_wen;
294+
end
305295
end
306296

307297
always_ff @(posedge clk) begin
308-
leds[0] <= halt_sig;
309-
if (program_counter == fail[0]) begin
310-
halt_sig <= 0;
311-
leds[5:1] <= 5'b11100;
312-
tx_word <= "fail";
313-
end else if (program_counter == pass[0]) begin
314-
leds[5:1] <= 5'b10101;
315-
halt_sig <= 0;
316-
tx_word <= "pass";
317-
end else begin
318-
leds[5:1] <= program_counter[6:2];
319-
tx_word[31:24] <= hex_to_ascii(program_counter[15:12]);
320-
tx_word[23:16] <= hex_to_ascii(program_counter[11:8]);
321-
tx_word[15:8] <= hex_to_ascii(program_counter[7:4]);
322-
tx_word[7:0] <= hex_to_ascii(program_counter[3:0]);
298+
if (1) begin // TODO: add hazard detection
299+
pr_mem_wb.ALU_OUT <= ALU_OUT;
300+
pr_mem_wb.DM_OUT <= DM_OUT;
301+
302+
pr_mem_wb.RF_wsel <= pr_ex_mem.RF_wsel;
303+
pr_mem_wb.RF_wen <= pr_ex_mem.RF_wen;
304+
pr_mem_wb.RF_wdata_sel <= pr_ex_mem.RF_wdata_sel;
323305
end
324306
end
325-
`endif
326307

327308
endmodule

‎src/misc/synth.v

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,75 @@
1+
2+
//$display("pc: %h, alu: %h", program_counter, ALU_OUT);
3+
if(program_counter == 32'h80000100) begin
4+
5+
/*
6+
for(int i=0; i<640; i=i+1) begin
7+
$display("mem: %h", dm.mem[32'h960+i]);
8+
end
9+
*/
10+
11+
end
12+
13+
14+
15+
/*
16+
if (mem_sel == 2'b11 && RF_wdata_sel == `RF_WDATA_SEL_DM && RF_wen)
17+
$display(
18+
"WHY THE FUCK YOU ARE HERE, mem_sel=%b, %b %b %b %b, %h",
19+
mem_sel,
20+
sig_read_im,
21+
sig_data_read,
22+
sig_compute,
23+
sig_write_back,
24+
ALU_OUT
25+
);
26+
*/
27+
28+
29+
30+
/*
31+
assign leds[5:0] = program_counter[7:2];
32+
*/
33+
34+
`ifdef synth
35+
36+
logic [31:0] gp;
37+
logic [31:0] tx_word;
38+
assign gp[31:0] = rf.registers[3];
39+
40+
function [7:0] hex_to_ascii;
41+
input [3:0] hex_digit_1;
42+
begin
43+
if ({4'b0, hex_digit_1} < 8'd10) hex_to_ascii = "0" + {4'b0, hex_digit_1};
44+
else hex_to_ascii = "A" + ({4'b0, hex_digit_1} - 8'd10);
45+
end
46+
endfunction
47+
48+
logic [31:0] pass[1];
49+
logic [31:0] fail[1];
50+
51+
initial begin
52+
//$readmemh("../../mem_files/rv32ui-p-tests/rv32ui-p-sw_pass.txt", pass);
53+
//$readmemh("../../mem_files/rv32ui-p-tests/rv32ui-p-sw_fail.txt", fail);
54+
leds[5:1] = 5'b00000;
55+
end
56+
57+
always_ff @(posedge clk) begin
58+
leds[0] <= halt_sig;
59+
if (program_counter == fail[0]) begin
60+
halt_sig <= 0;
61+
leds[5:1] <= 5'b11100;
62+
tx_word <= "fail";
63+
end else if (program_counter == pass[0]) begin
64+
leds[5:1] <= 5'b10101;
65+
halt_sig <= 0;
66+
tx_word <= "pass";
67+
end else begin
68+
leds[5:1] <= program_counter[6:2];
69+
tx_word[31:24] <= hex_to_ascii(program_counter[15:12]);
70+
tx_word[23:16] <= hex_to_ascii(program_counter[11:8]);
71+
tx_word[15:8] <= hex_to_ascii(program_counter[7:4]);
72+
tx_word[7:0] <= hex_to_ascii(program_counter[3:0]);
73+
end
74+
end
75+
`endif

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