FPGA basics

Basic usage

• Required tools:
  • Verilator - Simulation
  • Yosys - for general synth
  • nextpnr - Place and Route
  • gowin_pack - Creating packed version for tangnano20k
  • openFPGALoader - For loading into FPGA

For simulation verilator is enough.

cmake -S . -B build-sim/
cmake --build build-sim/
./build-sim/UART_Test

Top level Makefile can be used for both synth and sim

make synth-all
make sim-run

Project Aims

• Single cycle core
• rv32ui-p tests
• FPGA BSRAM usage
• Memory mapped I/O
• run binaries on core
• UART "echo server"
• pipelining
• UART calculator
• Documentation
• Interrupts
• ...

TODO

• create a libc-like (maybe use newlib)
• why first uploads are iffy
• find a efficient way to put things other than .rodata.str1.1 to sram
• why read is so slow
• i2c
• fix leds, use buttons for reset