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    72 repositories

    • dau-build

      Public
      Build tools for dau projects
      Python
      •
      Apache License 2.0
      •0•0•0•1•Updated Apr 17, 2025Apr 17, 2025

    • tools

      Public
      Software Tools
      Makefile
      •
      Apache License 2.0
      •0•1•0•0•Updated Apr 17, 2025Apr 17, 2025

    • verilator-python

      Public
      Python/PyPI wrapper for Verilator
      hardwareverilogsystemverilogverilator
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Apr 15, 2025Apr 15, 2025

    • artlink

      Public
      A package for packaging, organizing, and combining artifacts
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Apr 14, 2025Apr 14, 2025

    • vivado-docker

      Public
      Minimal Dockerized Vivado
      fpgahardwarevhdlverilogvivadosystemverilogverilog-hdl
      Shell
      •
      Apache License 2.0
      •0•1•0•0•Updated Apr 14, 2025Apr 14, 2025

    • amaranth-boards

      Public
      Board definitions for Amaranth HDL
      Python
      •
      BSD 2-Clause "Simplified" License
      •114•0•0•0•Updated Apr 4, 2025Apr 4, 2025

    • nitefury-notes

      Public
      Notes setting up / using NiteFury
      Python
      •0•1•0•0•Updated Apr 2, 2025Apr 2, 2025

    • litex

      Public
      Build your hardware, easily!
      C
      •
      Other
      •613•0•0•0•Updated Mar 29, 2025Mar 29, 2025

    • litesdcard

      Public
      Small footprint and configurable SDCard core
      Python
      •
      Other
      •36•0•0•0•Updated Mar 28, 2025Mar 28, 2025

    • litei2c

      Public
      Small footprint and configurable I2C core
      Python
      •
      BSD 2-Clause "Simplified" License
      •3•0•0•0•Updated Mar 27, 2025Mar 27, 2025

    • amaranth

      Public
      A modern hardware definition language and toolchain based on Python
      Python
      •
      BSD 2-Clause "Simplified" License
      •177•0•0•0•Updated Mar 27, 2025Mar 27, 2025

    • uhdm-pypi

      Public
      PyPI Packaging for UHDM
      CMake
      •
      Apache License 2.0
      •0•0•0•0•Updated Dec 25, 2024Dec 25, 2024

    • litex-boards

      Public
      LiteX boards files
      Python
      •
      BSD 2-Clause "Simplified" License
      •310•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • litepcie

      Public
      Small footprint and configurable PCIe core
      Python
      •
      Other
      •127•1•0•0•Updated Dec 18, 2024Dec 18, 2024

    • litespi

      Public
      Small footprint and configurable SPI core
      Python
      •
      BSD 2-Clause "Simplified" License
      •23•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • synlig

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •26•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • basejump_stl

      Public
      BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      •
      Other
      •105•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • systemverilog-plugin

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •26•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • dma_ip_drivers

      Public
      Xilinx QDMA IP Drivers
      C
      •449•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • brevitas

      Public
      Brevitas: neural network quantization in PyTorch
      Python
      •
      Other
      •210•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • nextpnr-xilinx

      Public
      Experimental flows using nextpnr for Xilinx devices
      C++
      •
      ISC License
      •48•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • openFPGALoader

      Public
      Universal utility for programming FPGA
      C++
      •
      Apache License 2.0
      •287•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • amaranth-soc

      Public
      System on Chip toolkit for Amaranth HDL
      Python
      •
      BSD 2-Clause "Simplified" License
      •34•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • cocotb

      Public
      cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •544•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • UHDM

      Public
      Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •41•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •929•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • RapidWright

      Public
      Build Customized FPGA Implementations for Vivado
      Java
      •
      Other
      •114•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • prjxray

      Public
      Documenting the Xilinx 7-series bit-stream format.
      Python
      •
      ISC License
      •156•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •653•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •160•0•0•0•Updated Dec 18, 2024Dec 18, 2024