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    32 repositories

    • garnet

      Public
      Next generation CGRA generator
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •11•106•81•3•Updated Nov 18, 2024Nov 18, 2024

    • aha

      Public
      Python
      •8•51•7•15•Updated Nov 18, 2024Nov 18, 2024

    • lake

      Public
      Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •2•19•7•6•Updated Nov 16, 2024Nov 16, 2024

    • canal

      Public
      Python
      •1•6•0•1•Updated Nov 7, 2024Nov 7, 2024

    • Halide-to-Hardware

      Public
      C++
      •
      Other
      •12•78•30•0•Updated Nov 6, 2024Nov 6, 2024

    • aha_tutorial

      Public
      Aha Tutorial
      SCSS
      •0•0•0•0•Updated Nov 3, 2024Nov 3, 2024

    • archipelago

      Public
      Python
      •2•0•0•0•Updated Sep 5, 2024Sep 5, 2024

    • lassen

      Public
      The PE for the second generation CGRA (garnet).
      Python
      •4•16•24•5•Updated Sep 4, 2024Sep 4, 2024

    • clockwork

      Public
      A polyhedral compiler for hardware accelerators
      C++
      •12•0•0•0•Updated Jul 29, 2024Jul 29, 2024

    • AhaM3SoC

      Public
      SoC Based on ARM Cortex-M3
      Verilog
      •
      Apache License 2.0
      •10•25•1•1•Updated May 17, 2024May 17, 2024

    • aha-wiki-page

      Public
      1•0•0•0•Updated Feb 1, 2024Feb 1, 2024

    • doc

      Public
      Papers, Posters, Presentations, Documentation...
      5•18•0•0•Updated Jan 9, 2024Jan 9, 2024

    • gemstone

      Public
      Python
      •3•10•2•3•Updated Sep 5, 2023Sep 5, 2023

    • aha-flow-app

      Public
      JavaScript
      •1•1•0•7•Updated Mar 3, 2023Mar 3, 2023

    • Configuration

      Public
      SystemVerilog
      •
      BSD 3-Clause "New" or "Revised" License
      •0•1•0•0•Updated Oct 5, 2022Oct 5, 2022

    • amber_demo

      Public
      JTAG/Python/M3 code for Amber demo
      0•0•0•0•Updated May 20, 2022May 20, 2022

    • pdq

      Public
      Python
      •0•0•1•3•Updated Oct 26, 2021Oct 26, 2021

    • onyx

      Public
      Tcl
      •
      BSD 3-Clause "New" or "Revised" License
      •1•3•0•0•Updated Oct 10, 2021Oct 10, 2021

    • CGRAFlowDoc

      Public
      Documentation for the entire CGRAFlow
      2•18•0•0•Updated Sep 17, 2021Sep 17, 2021

    • amber-vde

      Public
      Tcl
      •0•1•0•0•Updated Aug 23, 2020Aug 23, 2020

    • GenClockTrials

      Public
      Design with Generated Clocks
      Tcl
      •0•0•0•0•Updated May 20, 2020May 20, 2020

    • GarnetFlow

      Public archive
      Shell
      •0•2•2•5•Updated Mar 11, 2020Mar 11, 2020

    • CGRAFlow

      Public
      Integration test for entire CGRA flow
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •2•12•21•0•Updated Jan 17, 2020Jan 17, 2020

    • hammer_implementation_flow

      Public
      Python
      •1•1•0•0•Updated Oct 24, 2019Oct 24, 2019

    • chipyard

      Public
      Pre-release starter template for custom Chisel projects
      C
      •
      Other
      •654•2•0•0•Updated Oct 5, 2019Oct 5, 2019

    • Applications

      Public
      The applications for the Stanford AHA CGRA
      C++
      •2•3•0•0•Updated Jun 2, 2019Jun 2, 2019

    • delta

      Public
      Python
      •0•0•0•0•Updated May 2, 2019May 2, 2019

    • CGRAMapper

      Public
      CoreIR based mapping tool for CGRA
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •4•6•15•1•Updated Apr 25, 2019Apr 25, 2019

    • PowerDomainDesign

      Public archive
      Verilog
      •5•7•0•0•Updated Apr 11, 2019Apr 11, 2019

    • Primitives

      Public
      Official Repo for keeping track of and defining all primitives.
      BSD 3-Clause "New" or "Revised" License
      •0•2•2•0•Updated Jan 11, 2019Jan 11, 2019