Missing Zicsr Instruction Error

[JamesTimothyMeech]

When I try to run python3 OrangeCrab-bitstream.py on Ubuntu 22.04 I get this error:

INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 5).
make: Entering directory '/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/build/orangecrab/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/build/orangecrab/software/libcompiler_rt'
make: Entering directory '/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/build/orangecrab/software/libbase'
 CC       crt0.o
/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/cores/cpu/vexriscv/crt0.S: Assembler messages:
/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/cores/cpu/vexriscv/crt0.S:59: Error: unrecognized opcode `csrw mtvec,a0', extension `zicsr' required
/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/cores/cpu/vexriscv/crt0.S:85: Error: unrecognized opcode `csrw mie,a0', extension `zicsr' required
make: *** [/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/software/libbase/Makefile:45: crt0.o] Error 1
make: Leaving directory '/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/build/orangecrab/software/libbase'
Traceback (most recent call last):
  File "/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/OrangeCrab-bitstream.py", line 463, in <module>
    main()
  File "/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/OrangeCrab-bitstream.py", line 404, in main
    soc.PackageFirmware(builder)
  File "/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/OrangeCrab-bitstream.py", line 358, in PackageFirmware
    builder._generate_rom_software(compile_bios=False)
  File "/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/integration/builder.py", line 190, in _generate_rom_software
    subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
  File "/usr/lib/python3.10/subprocess.py", line 369, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', '/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/build/orangecrab/software/libbase', '-f', '/home/james/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/software/libbase/Makefile']' returned non-zero exit status 2.

What is the most sensible step for me to take to fix this?

I have seen advice to add _ziscr to the -march flag here: efabless/caravel_board#37 but LiteX regenerates the variables.mak file each time I run python3 OrangeCrab-bitstream.py which means I cannot tell if my fix has done anything.

[JamesTimothyMeech]

Trying again on my Mac instead produces a different error:

INFO:SoC:--------------------------------------------------------------------------------
Traceback (most recent call last):
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/OrangeCrab-bitstream.py", line 466, in <module>
    main()
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/OrangeCrab-bitstream.py", line 401, in main
    soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)),**argdict(args))
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/OrangeCrab-bitstream.py", line 267, in __init__
    SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, csr_data_width=32,**kwargs)
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/integration/soc_core.py", line 153, in __init__
    self.add_controller("ctrl")
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/integration/soc.py", line 799, in add_controller
    setattr(self.submodules, name, SoCController(**kwargs))
                                   ^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/integration/soc.py", line 670, in __init__
    self._reset = CSRStorage(1, description="""Any write to this register will reset the SoC.""")
                  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/interconnect/csr.py", line 383, in __init__
    _CompoundCSR.__init__(self, size, name)
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/interconnect/csr.py", line 131, in __init__
    _CSRBase.__init__(self, size, name)
  File "/Users/jamesmeech/Desktop/Casino/OrangeCrab-test-sw/hw/deps/litex/litex/soc/interconnect/csr.py", line 50, in __init__
    raise ValueError("Cannot extract CSR name from code, need to specify.")
ValueError: Cannot extract CSR name from code, need to specify.```

[JamesTimothyMeech]

I'm going to attempt to create a working example by integrating the ADC parts from https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py into https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/gsd_orangecrab.py which works out of the box for me

[JamesTimothyMeech]

This is what I have so far: adcCrab.txt. LiteX will happily build this without errors and load it to the orangecrab with python3 adcCrab.py --device 85F --cpu-type femtorv --cpu-variant gracilis --with-spi-sdcard --build --load but unfortunately when I try to run the catalog command in LiteOs: https://github.com/BrunoLevy/learn-fpga/tree/master/LiteX/software/LiteOS which I am using to load programs onto the LiteX generated system on chip the program hangs. I think some of the stuff in the file is interfering with the SPI SD card but I'm struggling to figure out what even after commenting out a large amount of the code. I can see that the asense is getting into the LiteX generated CSRs which is good because I want to be able to access the ADC. Any pointers to resources or obvious mistakes in my code would be greatly appreciated!

[JamesTimothyMeech]

I switched my project over to the Arty and I am using LiteX with its hardware ADC block for now

[gregdavill]

For anyone seeing this issue, the first issue relating to Zicsr is a bitrot. Modern GCC requires that you append _zicsr to the march string in order to add in csr opcodes

The second issue looks like a liteX version bug. This test software was compiled when needed and hasn't needed to be updated since, so as you can see it has bitrotted a bit.