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verilator Public
Forked from verilator/verilatorVerilator open-source SystemVerilog simulator and lint system
SystemVerilog Other UpdatedAug 15, 2026 -
xezim Public
Forked from aionhw/xezimRust SystemVerilog simulator (IEEE1800-2023/2017) with UVM1.2 /1800.2-2020, VPI, DPI-C, XTrace waveform support
Rust Apache License 2.0 UpdatedAug 15, 2026 -
xezim-core Public
Forked from aionhw/xezim-coreSystemVerilog Frontend for simulator
Rust Apache License 2.0 UpdatedAug 8, 2026 -
sv-tests Public
Forked from chipsalliance/sv-testsTest suite designed to check compliance with the SystemVerilog standard.
SystemVerilog ISC License UpdatedAug 3, 2026
