Changes to increase capabilities of long readouts and programs #305
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Change in asm_v2 adding virtual sweep registers. Adding CloseLoopV2 and OpenLoopV2 to allow reuse of loop increment register. Modifying add_reg method in asm_v2 to create virtual registers with a specific depth. virtual registers occupy addresses from self.soccfg['tprocs'][0]['dreg_qty'] - 1 to self.soccfg['tprocs'][0]['dreg_qty'] - 1 - depth (included). There is a roll over these registers that get rewritten. Suppressing the register initalization after preprocess and before translate (WriteReg(dst=k,src=v.init.start).translate(self)). This is to accomodate the creation of virtual registers that are assigned during the translate phase. Adding some modified firmwares with extended program and data memory and one extended avg buffer memory to 2**16 words. Modified the __init__.py to expose QickProgramV2, AcquireProgramV2, QickRegisterV2, AcquireMixin classes.
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Change in asm_v2 adding virtual sweep registers.
Adding CloseLoopV2 and OpenLoopV2 to allow reuse of loop increment register. Modifying add_reg method in asm_v2 to create virtual registers with a specific depth. virtual registers occupy addresses from self.soccfg['tprocs'][0]['dreg_qty'] - 1 to self.soccfg['tprocs'][0]['dreg_qty'] - 1 - depth (included). There is a roll over these registers that get rewritten. Suppressing the register initalization after preprocess and before translate (WriteReg(dst=k,src=v.init.start).translate(self)). This is to accomodate the creation of virtual registers that are assigned during the translate phase.
Adding some modified firmwares with extended program and data memory and one extended avg buffer memory to 2**16 words.
Modified the init.py to expose QickProgramV2, AcquireProgramV2, QickRegisterV2, AcquireMixin classes.