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@jatin-bhateja jatin-bhateja commented Mar 31, 2025

  • Intel AVX10[1] extends and enhances the capabilities of Intel AVX-512 to benefit all Intel® products and will be the vector ISA of choice moving into the future.
  • It supports a new ISA versioning scheme which simplifies the existing AVX512 feature enumeration scheme. Feature set supported by an AVX10 ISA version will be supported by all the versions above it.
  • The initial, fully-featured version of Intel® AVX10 will be enumerated as Version 2 (denoted as Intel® AVX10.2). This will include the new ISA extension over the existing AVX512 instructions.
  • An early version of Intel® AVX10 (Version 1, or Intel® AVX10.1) that only enumerates the Intel® AVX-512 instruction set at 128, 256, and 512 bits will be enabled on the Granite Rapids Server for software pre-enabling.

This patch adds the necessary CPUID feature detection for AVX10 ISA version 1 and 2. In terms of architectural state save restoration, AVX10 is isomorphic to AVX512 support up till Granite Rapids. State components affected by AVX10 extension include SSE, AVX, Opmask, ZMM_Hi256, and Hi16_ZMM registers.

The patch has been regressed through tier1 and jvmci tests

Please review and share your feedback.

Best Regards,
Jatin

[1] https://www.intel.com/content/www/us/en/content-details/844829/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html


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  • JDK-8352675: Support Intel AVX10 converged vector ISA feature detection (Enhancement - P4)

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/label add hotspot-compiler-dev

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bridgekeeper bot commented Mar 31, 2025

👋 Welcome back jbhateja! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

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@jatin-bhateja This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

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8352675: Support Intel AVX10 converged vector ISA feature detection

Reviewed-by: sviswanathan, vlivanov, yzheng

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@openjdk openjdk bot added the hotspot-compiler hotspot-compiler-dev@openjdk.org label Mar 31, 2025
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The hotspot-compiler label was successfully added.

@jatin-bhateja jatin-bhateja marked this pull request as ready for review April 2, 2025 18:56
@openjdk openjdk bot added the rfr Pull request is ready for review label Apr 2, 2025
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openjdk bot commented Apr 3, 2025

@jatin-bhateja Please do not rebase or force-push to an active PR as it invalidates existing review comments. Note for future reference, the bots always squash all changes into a single commit automatically as part of the integration. See OpenJDK Developers’ Guide for more information.

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Just leaving a few drive-by comments, I'm really not very familiar with this code. It would be nice if someone from Intel reviewed this also.

Also: you should probably update some more copyright dates ;)

int res = jio_snprintf(
buf, sizeof(buf),
"(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x",
cores_per_cpu(), threads_per_core(),
cpu_family(), _model, _stepping, os::cpu_microcode_revision());
assert(res > 0, "not enough temporary space allocated");
insert_features_names(buf + res, sizeof(buf) - res, _features_names);
insert_features_names(_features, buf + res, sizeof(buf) - res, _features_names);
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x86 is the only platform which uses insert_features_names. Other platforms rely on macros. Maybe it's time to do the same on x86?

@@ -56,6 +56,9 @@ class Abstract_VM_Version: AllStatic {

// CPU feature flags, can be affected by VM settings.
static uint64_t _features;
// Extra CPU feature flags used when all 64 bits of _features are exhausted for
// on a given target, currently only used for x86_64, can be affected by VM settings.
static uint64_t _extra_features;
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That's unfortunate. Maybe it's time to turn _features into a fixed size (platform-specific) bitmap instead? (RegMask is one existing example.) Having 2 independent fields is error-prone (look at _cpu_features).

@jatin-bhateja jatin-bhateja marked this pull request as draft April 16, 2025 16:01
@openjdk openjdk bot removed the rfr Pull request is ready for review label Apr 16, 2025
@jatin-bhateja jatin-bhateja marked this pull request as ready for review April 23, 2025 05:40
@openjdk openjdk bot added the rfr Pull request is ready for review label Apr 23, 2025
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/label add graal-dev

@openjdk openjdk bot added the graal graal-dev@openjdk.org label Apr 23, 2025
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The graal label was successfully added.

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It looks much better! Thanks, Jatin.

I'm curious why don't you represent feature bitmap as a POD (with all the accessors on it) and pass it around by value when needed? (It's size will vary across platforms, but will be fixed at runtime.) It should significantly simplify the implementation.

As an example, take a look at RegMask in C2. It accommodates significantly more bits than needed for VM_Version.

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It looks much better! Thanks, Jatin.

I'm curious why don't you represent feature bitmap as a POD (with all the accessors on it) and pass it around by value when needed? (It's size will vary across platforms, but will be fixed at runtime.) It should significantly simplify the implementation.

As an example, take a look at RegMask in C2. It accommodates significantly more bits than needed for VM_Version.

Hi @iwanowww,
RegMask is part of opto code, and it may not be accessible to the JVMCI interface, Currently, JVMCI captures the native address of various fields of VM_Struct, which are of interest to Graal. In the proposed solution, we are adding a new dynamically sized feature vector whose each element is 64 bits wide. JVMCI book-keeps the dynamic feature vector and its size, then uses the UNSAFE access API to compute the enabled feature set on the Java side.

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RegMask is part of opto code, and it may not be accessible to the JVMCI interface

I'm not suggesting to reuse RegMask, but introduce a separate class (e.g., VMFeatures) and embed its instances into Abstract_VM_Version (as VMFeatures _features and VMFeatures _cpu_features). You can keep all the accessors and bit manipulation logic on VMFeatures class.

JVMCI can still operate on in-memory representation at Abstract_VM_Version::_features. But it now needs to query its size (which becomes platform-specific constant).

(BTW all CPU feature constants in AMD64HotSpotVMConfig change their meaning. I don't see any usages in JDK code. Should they go away now?)


class VM_Features {
public:
using FeatureVector = uint64_t [MAX_FEATURE_VEC_SIZE];
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Do you think it would be better to refactor this into a separate class analogous to std::bitset? You can start with only implementing test, set, reset. This would help in other use cases, too.

https://en.cppreference.com/w/cpp/utility/bitset

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In essence, what we have currently is a bitmap implementation, but its utility is limited to VM_Version for now. The current approach simplifies the JVMCI side of handling. We have an existing utility for bitset src/hotspot/share/utilities/bitMap.hpp, we have multiple implementations for feature detection currently for different targets, it will be good to have the unified solution in the future. For now our intent is just to lift the hard limation of 64 feature bits for x86 target.

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Very nice!

I made a cleanup pass over the code [1]. Feel free to incorporate it or let me know if you have any questions/concerns.

Meanwhile, submitted it for testing.

[1] iwanowww@35aeb88

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JVMCI changes look good. Will run some Graal tests on this PR

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There are some SA-related failures. Fixed by [1]. Otherwise, testing results are good.

[1] iwanowww@9d4b85a

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Testing results (hs-tier1 - hs-tier4) are clean.

@openjdk openjdk bot added the ready Pull request is ready to be integrated label May 8, 2025
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CPU features in Graal remain the same after this PR. Passed all Graal compiler unit tests.

@@ -452,13 +461,11 @@ class VM_Version_StubGenerator: public StubCodeGenerator {
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
__ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
__ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
__ cmpl(rcx, 0x18000000);
__ jccb(Assembler::notEqual, done); // jump if AVX is not supported
__ jccb(Assembler::equal, done); // jump if AVX is not supported
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This and all the following places with multi-bit check still need to be fixed. If you walk through stock and new code in this PR when Address(rsi, 8) on line 468 has 0x10000000, you will observe that stock code will jump to done and new code will not jump to done. Let me know if I am missing something.

@openjdk openjdk bot removed the ready Pull request is ready to be integrated label May 9, 2025
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Rest of the PR looks good to me.

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Looks good to me.

@openjdk openjdk bot added the ready Pull request is ready to be integrated label May 9, 2025
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Thanks @iwanowww , @sviswa7 , @mur47x111 , @merykitty for your reviews.

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/integrate

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openjdk bot commented May 9, 2025

Going to push as commit 3b336a9.
Since your change was applied there have been 15 commits pushed to the master branch:

Your commit was automatically rebased without conflicts.

@openjdk openjdk bot added the integrated Pull request has been integrated label May 9, 2025
@openjdk openjdk bot closed this May 9, 2025
@openjdk openjdk bot removed ready Pull request is ready to be integrated rfr Pull request is ready for review labels May 9, 2025
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openjdk bot commented May 9, 2025

@jatin-bhateja Pushed as commit 3b336a9.

💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored.

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