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8334078: RISC-V: TestIntVect.java fails after JDK-8332153 when running without RVV #19686

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8334078: RISC-V: TestIntVect.java fails after JDK-8332153 when running without RVV #19686

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9ead6b1
8334078: TestIntVect.java fails without RVV after JDK-8332153
Jun 13, 2024
be04472
Simplify strcat
Jun 13, 2024
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5 changes: 4 additions & 1 deletion src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,10 @@ void VM_Version::setup_cpu_available_features() {
if (_feature_list[i]->feature_string()) {
const char* tmp = _feature_list[i]->pretty();
if (strlen(tmp) == 1) {
strcat(buf, " ");
// Feature string is expected to be in multi-character form
// like rvc, rvv, etc so that it will be easier to specify
// target feature string in tests.
strcat(buf, " rv");
strcat(buf, tmp);
} else {
// Feature string is expected to be lower case.
Expand Down
117 changes: 19 additions & 98 deletions test/hotspot/jtreg/compiler/c2/cr7200264/TestIntVect.java
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Expand Up @@ -480,10 +480,7 @@ void test_suba(int[] a0, int[] a1, int[] a2) {

@Test
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_mulc(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]*VALUE);
Expand All @@ -492,10 +489,7 @@ void test_mulc(int[] a0, int[] a1) {

@Test
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.SUB_VI, "> 0", IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_mulc_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]*(-VALUE));
Expand Down Expand Up @@ -527,15 +521,7 @@ void test_mula(int[] a0, int[] a1, int[] a2) {
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true"})
@IR(counts = { IRNode.ADD_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.RSHIFT_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true", "rvv", "true"})
// Not vectorized: On aarch64, vectorization for this example results in
// MulVL nodes, which asimd does not support.
@IR(counts = { IRNode.LOAD_VECTOR_I, "= 0",
Expand All @@ -555,15 +541,7 @@ void test_divc(int[] a0, int[] a1) {
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true"})
@IR(counts = { IRNode.ADD_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.RSHIFT_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0",
IRNode.SUB_VI,
IRNode.VECTOR_SIZE + "min(max_int, max_long)", "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"avx2", "true", "sve", "true", "rvv", "true"})
// Not vectorized: On aarch64, vectorization for this example results in
// MulVL nodes, which asimd does not support.
@IR(counts = { IRNode.LOAD_VECTOR_I, "= 0",
Expand Down Expand Up @@ -683,10 +661,7 @@ void test_xora(int[] a0, int[] a1, int[] a2) {

@Test
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_sllc(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<VALUE);
Expand All @@ -695,10 +670,7 @@ void test_sllc(int[] a0, int[] a1) {

@Test
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_sllc_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<(-VALUE));
Expand All @@ -710,12 +682,7 @@ void test_sllc_n(int[] a0, int[] a1) {
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_sllc_o(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<SHIFT);
Expand All @@ -727,12 +694,7 @@ void test_sllc_o(int[] a0, int[] a1) {
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_sllc_on(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<(-SHIFT));
Expand All @@ -741,10 +703,7 @@ void test_sllc_on(int[] a0, int[] a1) {

@Test
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.LSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_sllv(int[] a0, int[] a1, int b) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]<<b);
Expand All @@ -753,10 +712,7 @@ void test_sllv(int[] a0, int[] a1, int b) {

@Test
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srlc(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>VALUE);
Expand All @@ -765,10 +721,7 @@ void test_srlc(int[] a0, int[] a1) {

@Test
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srlc_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>(-VALUE));
Expand All @@ -780,12 +733,7 @@ void test_srlc_n(int[] a0, int[] a1) {
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srlc_o(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>SHIFT);
Expand All @@ -797,12 +745,7 @@ void test_srlc_o(int[] a0, int[] a1) {
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srlc_on(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>(-SHIFT));
Expand All @@ -811,10 +754,7 @@ void test_srlc_on(int[] a0, int[] a1) {

@Test
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.URSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srlv(int[] a0, int[] a1, int b) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>>b);
Expand All @@ -823,10 +763,7 @@ void test_srlv(int[] a0, int[] a1, int b) {

@Test
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srac(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>VALUE);
Expand All @@ -835,10 +772,7 @@ void test_srac(int[] a0, int[] a1) {

@Test
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srac_n(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>(-VALUE));
Expand All @@ -850,12 +784,7 @@ void test_srac_n(int[] a0, int[] a1) {
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srac_o(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>SHIFT);
Expand All @@ -867,12 +796,7 @@ void test_srac_o(int[] a0, int[] a1) {
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "= 0",
IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srac_on(int[] a0, int[] a1) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>(-SHIFT));
Expand All @@ -881,10 +805,7 @@ void test_srac_on(int[] a0, int[] a1) {

@Test
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true"})
@IR(counts = { IRNode.RSHIFT_VI, "> 0" },
applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"})
applyIfCPUFeatureOr = {"sse2", "true", "asimd", "true", "rvv", "true"})
void test_srav(int[] a0, int[] a1, int b) {
for (int i = 0; i < a0.length; i+=1) {
a0[i] = (int)(a1[i]>>b);
Expand Down
2 changes: 1 addition & 1 deletion test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeURShiftSubword.java
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Expand Up @@ -35,7 +35,7 @@
* @key randomness
* @summary Auto-vectorization enhancement for unsigned shift right on signed subword types
* @requires ((os.arch=="amd64" | os.arch=="x86_64") & (vm.opt.UseSSE == "null" | vm.opt.UseSSE > 3)) | os.arch=="aarch64" |
* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
* (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
* @library /test/lib /
* @run driver compiler.c2.irTests.TestVectorizeURShiftSubword
*/
Expand Down
2 changes: 1 addition & 1 deletion test/hotspot/jtreg/compiler/intrinsics/TestBitShuffleOpers.java
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Expand Up @@ -31,7 +31,7 @@
* (vm.cpu.features ~= ".*bmi2.*" & vm.cpu.features ~= ".*bmi1.*" &
* vm.cpu.features ~= ".*sse2.*")) |
* (os.arch=="aarch64" & vm.cpu.features ~= ".*svebitperm.*") |
* (os.arch=="riscv64" & vm.cpu.features ~= ".*v,.*"))
* (os.arch=="riscv64" & vm.cpu.features ~= ".*rvv.*"))
* @library /test/lib /
* @run driver compiler.intrinsics.TestBitShuffleOpers
*/
Expand Down
20 changes: 8 additions & 12 deletions test/hotspot/jtreg/compiler/intrinsics/chacha/TestChaCha20.java
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Expand Up @@ -38,7 +38,7 @@
* @library /test/lib
* @requires (vm.cpu.features ~= ".*avx512.*" | vm.cpu.features ~= ".*avx2.*" | vm.cpu.features ~= ".*avx.*") |
* (os.arch=="aarch64" & vm.cpu.features ~= ".*simd.*") |
* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
* (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
* @build compiler.intrinsics.chacha.ExerciseChaCha20
* jdk.test.whitebox.WhiteBox
* @run driver jdk.test.lib.helpers.ClassFileInstaller jdk.test.whitebox.WhiteBox
Expand All @@ -60,13 +60,9 @@ private static List<String> mix(List<String> o, String... mix) {
return n;
}

private static boolean containsFuzzy(List<String> list, String sub, Boolean matchExactly) {
private static boolean containsFuzzy(List<String> list, String sub) {
for (String s : list) {
if (matchExactly) {
if (s.equals(sub)) return true;
} else {
if (s.contains(sub)) return true;
}
if (s.contains(sub)) return true;
}
return false;
}
Expand All @@ -86,27 +82,27 @@ public static void main(String... args) throws Exception {
}

// Otherwise, select the tests that make sense on current platform.
if (containsFuzzy(cpuFeatures, "avx512", false)) {
if (containsFuzzy(cpuFeatures, "avx512")) {
System.out.println("Setting up AVX512 worker");
configs.add(List.of("-XX:UseAVX=3"));
}
if (containsFuzzy(cpuFeatures, "avx2", false)) {
if (containsFuzzy(cpuFeatures, "avx2")) {
System.out.println("Setting up AVX2 worker");
configs.add(List.of("-XX:UseAVX=2"));
}
if (containsFuzzy(cpuFeatures, "avx", false)) {
if (containsFuzzy(cpuFeatures, "avx")) {
System.out.println("Setting up AVX worker");
configs.add(List.of("-XX:UseAVX=1"));
}
} else if (Platform.isAArch64()) {
// AArch64 intrinsics require the advanced simd instructions
if (containsFuzzy(cpuFeatures, "simd", false)) {
if (containsFuzzy(cpuFeatures, "simd")) {
System.out.println("Setting up ASIMD worker");
configs.add(new ArrayList());
}
} else if (Platform.isRISCV64()) {
// Riscv64 intrinsics require the vector instructions
if (containsFuzzy(cpuFeatures, "v", true)) {
if (containsFuzzy(cpuFeatures, "rvv")) {
System.out.println("Setting up vector worker");
configs.add(List.of("-XX:+UseRVV"));
}
Expand Down
2 changes: 1 addition & 1 deletion test/hotspot/jtreg/compiler/lib/ir_framework/test/IREncodingPrinter.java
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Expand Up @@ -108,7 +108,7 @@ public class IREncodingPrinter {
"asimd",
"sve",
// Riscv64
"v",
"rvv",
"zvbb"
));

Expand Down
2 changes: 1 addition & 1 deletion test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastRVV.java
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Expand Up @@ -34,7 +34,7 @@
* @modules jdk.incubator.vector
* @modules java.base/jdk.internal.misc
* @summary Test that vector cast intrinsics work as intended on riscv (rvv).
* @requires os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*"
* @requires os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*"
* @library /test/lib /
* @run main/timeout=300 compiler.vectorapi.reshape.TestVectorCastRVV
*/
Expand Down
2 changes: 1 addition & 1 deletion test/hotspot/jtreg/compiler/vectorization/TestSignumVector.java
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Expand Up @@ -28,7 +28,7 @@
* and riscv64 (vector)
* @requires vm.compiler2.enabled
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx.*") | os.arch == "aarch64" |
* (os.arch == "riscv64" & vm.cpu.features ~= ".*v,.*")
* (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
* @library /test/lib /
* @run driver compiler.vectorization.TestSignumVector
*/
Expand Down
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