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8333964: RISC-V: C2: Check "requires_strict_order" flag for floating-point add reduction #19649

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8333964: RISC-V: C2: Check "requires_strict_order" flag for floating-point add reduction #19649

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73cfbfa
8333964: RISC-V: C2: Check "requires_strict_order" flag for floating-…
Jun 11, 2024
a7a809f
Enable AddReduction test for riscv rvv1.0
Jun 11, 2024
44cc665
Add some code comment
Jun 12, 2024
b87a36b
Polish Code Format
Jun 13, 2024
94a3648
Merge remote-tracking branch 'upstream/master' into JDK-8333964
Jun 17, 2024
67987f2
Update test cast condition
Jun 17, 2024
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42 changes: 38 additions & 4 deletions src/hotspot/cpu/riscv/riscv_v.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -2007,11 +2007,12 @@ instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
ins_pipe(pipe_slow);
%}

instruct reduce_addF(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
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instruct reduce_addF_ordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
predicate(n->as_Reduction()->requires_strict_order());
match(Set dst (AddReductionVF src1 src2));
effect(TEMP tmp);
ins_cost(VEC_COST);
format %{ "reduce_addF $dst, $src1, $src2\t# KILL $tmp" %}
format %{ "reduce_addF_ordered $dst, $src1, $src2\t# KILL $tmp" %}
ins_encode %{
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
Expand All @@ -2022,11 +2023,28 @@ instruct reduce_addF(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
ins_pipe(pipe_slow);
%}

instruct reduce_addD(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
instruct reduce_addF_unordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
predicate(!n->as_Reduction()->requires_strict_order());
match(Set dst (AddReductionVF src1 src2));
effect(TEMP tmp);
ins_cost(VEC_COST);
format %{ "reduce_addF_unordered $dst, $src1, $src2\t# KILL $tmp" %}
ins_encode %{
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
__ vfredusum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
as_VectorRegister($tmp$$reg));
__ vfmv_f_s($dst$$FloatRegister, as_VectorRegister($tmp$$reg));
%}
ins_pipe(pipe_slow);
%}

instruct reduce_addD_ordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
predicate(n->as_Reduction()->requires_strict_order());
match(Set dst (AddReductionVD src1 src2));
effect(TEMP tmp);
ins_cost(VEC_COST);
format %{ "reduce_addD $dst, $src1, $src2\t# KILL $tmp" %}
format %{ "reduce_addD_ordered $dst, $src1, $src2\t# KILL $tmp" %}
ins_encode %{
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
Expand All @@ -2037,6 +2055,22 @@ instruct reduce_addD(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
ins_pipe(pipe_slow);
%}

instruct reduce_addD_unordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
predicate(!n->as_Reduction()->requires_strict_order());
match(Set dst (AddReductionVD src1 src2));
effect(TEMP tmp);
ins_cost(VEC_COST);
format %{ "reduce_addD_unordered $dst, $src1, $src2\t# KILL $tmp" %}
ins_encode %{
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
__ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1$$FloatRegister);
__ vfredusum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg),
as_VectorRegister($tmp$$reg));
__ vfmv_f_s($dst$$FloatRegister, as_VectorRegister($tmp$$reg));
%}
ins_pipe(pipe_slow);
%}

// vector add reduction - predicated

instruct reduce_addI_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_V0 v0, vReg tmp) %{
Expand Down
10 changes: 10 additions & 0 deletions test/hotspot/jtreg/compiler/loopopts/superword/TestVectorFPReduction.java
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Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,11 @@ public static void main(String[] args) {
failOn = {"no_strict_order"},
applyIfCPUFeatureOr = {"sve", "true", "sse2", "true"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {"requires_strict_order", ">=1", IRNode.ADD_REDUCTION_VF, ">=1"},
failOn = {"no_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
private static void testAddReductionVF() {
float result = 1;
for (int i = 0; i < SIZE; i++) {
Expand All @@ -71,6 +76,11 @@ private static void testAddReductionVF() {
failOn = {"no_strict_order"},
applyIfCPUFeatureOr = {"sve", "true", "sse2", "true"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
counts = {"requires_strict_order", ">=1", IRNode.ADD_REDUCTION_VD, ">=1"},
failOn = {"no_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
private static void testAddReductionVD() {
double result = 1;
for (int i = 0; i < SIZE; i++) {
Expand Down
42 changes: 42 additions & 0 deletions test/hotspot/jtreg/compiler/vectorapi/TestVectorAddMulReduction.java
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Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,12 @@ public static void testFloatAddKernel(VectorSpecies SPECIES, float[] f) {
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
applyIf = {"MaxVectorSize", ">=8"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
applyIf = {"MaxVectorSize", ">=8"},
counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
failOn = {"requires_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
public static void testFloatAdd_64() {
testFloatAddKernel(FloatVector.SPECIES_64, fa);
}
Expand All @@ -91,6 +97,12 @@ public static void testFloatAdd_64() {
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
applyIf = {"MaxVectorSize", ">=16"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
applyIf = {"MaxVectorSize", ">=16"},
counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
failOn = {"requires_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
public static void testFloatAdd_128() {
testFloatAddKernel(FloatVector.SPECIES_128, fa);
}
Expand All @@ -101,6 +113,12 @@ public static void testFloatAdd_128() {
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
applyIf = {"MaxVectorSize", ">=32"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
applyIf = {"MaxVectorSize", ">=32"},
counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
failOn = {"requires_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
public static void testFloatAdd_256() {
testFloatAddKernel(FloatVector.SPECIES_256, fa);
}
Expand All @@ -111,6 +129,12 @@ public static void testFloatAdd_256() {
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
applyIf = {"MaxVectorSize", ">=64"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
applyIf = {"MaxVectorSize", ">=64"},
counts = {IRNode.ADD_REDUCTION_VF, ">=1", "no_strict_order", ">=1"},
failOn = {"requires_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
public static void testFloatAdd_512() {
testFloatAddKernel(FloatVector.SPECIES_512, fa);
}
Expand All @@ -130,6 +154,12 @@ public static void testDoubleAddKernel(VectorSpecies SPECIES, double[] d) {
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
applyIf = {"MaxVectorSize", ">=16"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
applyIf = {"MaxVectorSize", ">=16"},
counts = {IRNode.ADD_REDUCTION_VD, ">=1", "no_strict_order", ">=1"},
failOn = {"requires_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
public static void testDoubleAdd_128() {
testDoubleAddKernel(DoubleVector.SPECIES_128, da);
}
Expand All @@ -140,6 +170,12 @@ public static void testDoubleAdd_128() {
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
applyIf = {"MaxVectorSize", ">=32"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
applyIf = {"MaxVectorSize", ">=32"},
counts = {IRNode.ADD_REDUCTION_VD, ">=1", "no_strict_order", ">=1"},
failOn = {"requires_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
public static void testDoubleAdd_256() {
testDoubleAddKernel(DoubleVector.SPECIES_256, da);
}
Expand All @@ -150,6 +186,12 @@ public static void testDoubleAdd_256() {
applyIfCPUFeatureOr = {"asimd", "true", "sse2", "true"},
applyIf = {"MaxVectorSize", ">=64"},
phase = CompilePhase.PRINT_IDEAL)
@IR(applyIfPlatform = {"riscv64", "true"},
applyIfCPUFeature = {"v", "true"},
applyIf = {"MaxVectorSize", ">=64"},
counts = {IRNode.ADD_REDUCTION_VD, ">=1", "no_strict_order", ">=1"},
failOn = {"requires_strict_order"},
phase = CompilePhase.PRINT_IDEAL)
public static void testDoubleAdd_512() {
testDoubleAddKernel(DoubleVector.SPECIES_512, da);
}
Expand Down