8318158: RISC-V: implement roundD/roundF intrisics

openjdk · Oct 26, 2023 · 5a22e5c · 5a22e5c
1 parent eb7d972
commit 5a22e5c
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Showing 3 changed files with 31 additions and 6 deletions.
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -4222,15 +4222,16 @@ void MacroAssembler::zero_dcache_blocks(Register base, Register cnt, Register tm
 }
 
 #define FCVT_SAFE(FLOATCVT, FLOATSIG)                                                     \
-void MacroAssembler::FLOATCVT##_safe(Register dst, FloatRegister src, Register tmp) {     \
+void MacroAssembler::FLOATCVT##_safe(Register dst, FloatRegister src,                     \
+                                     RoundingMode rm, Register tmp) {                     \
   Label done;                                                                             \
   assert_different_registers(dst, tmp);                                                   \
   fclass_##FLOATSIG(tmp, src);                                                            \
   mv(dst, zr);                                                                            \
   /* check if src is NaN */                                                               \
   andi(tmp, tmp, 0b1100000000);                                                           \
   bnez(tmp, done);                                                                        \
-  FLOATCVT(dst, src);                                                                     \
+  FLOATCVT(dst, src, rm);                                                                 \
   bind(done);                                                                             \
 }
 

diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
@@ -1246,10 +1246,10 @@ class MacroAssembler: public Assembler {
   // e.g. convert from NaN, +Inf, -Inf to int, float, double
   // will trigger exception, we need to deal with these situations
   // to get correct results.
-  void fcvt_w_s_safe(Register dst, FloatRegister src, Register tmp = t0);
-  void fcvt_l_s_safe(Register dst, FloatRegister src, Register tmp = t0);
-  void fcvt_w_d_safe(Register dst, FloatRegister src, Register tmp = t0);
-  void fcvt_l_d_safe(Register dst, FloatRegister src, Register tmp = t0);
+  void fcvt_w_s_safe(Register dst, FloatRegister src, RoundingMode rm = RoundingMode::rtz, Register tmp = t0);
+  void fcvt_l_s_safe(Register dst, FloatRegister src, RoundingMode rm = RoundingMode::rtz, Register tmp = t0);
+  void fcvt_w_d_safe(Register dst, FloatRegister src, RoundingMode rm = RoundingMode::rtz, Register tmp = t0);
+  void fcvt_l_d_safe(Register dst, FloatRegister src, RoundingMode rm = RoundingMode::rtz, Register tmp = t0);
 
   // vector load/store unit-stride instructions
   void vlex_v(VectorRegister vd, Register base, Assembler::SEW sew, VectorMask vm = unmasked) {

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
@@ -8240,6 +8240,30 @@ instruct convN2I(iRegINoSp dst, iRegN src)
   ins_pipe(ialu_reg);
 %}
 
+instruct round_double_reg(iRegLNoSp dst, fRegD src) %{
+  match(Set dst (RoundD src));
+
+  format %{ "fcvt.l.d $dst, $src\t#@round_double_reg" %}
+
+  ins_encode %{
+    __ fcvt_l_d_safe(as_Register($dst$$reg), as_FloatRegister($src$$reg), Assembler::RoundingMode::rne);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
+instruct round_float_reg(iRegINoSp dst, fRegF src) %{
+  match(Set dst (RoundF src));
+
+  format %{ "fcvt.w.s  $dst, $src\t#@round_float_reg" %}
+
+  ins_encode %{
+    __ fcvt_w_s_safe(as_Register($dst$$reg), as_FloatRegister($src$$reg), Assembler::RoundingMode::rne);
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
 // Convert oop pointer into compressed form
 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
   match(Set dst (EncodeP src));