Fusesoc and linter #367
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Fusesoc and linter #367
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This fixes compilation issues with the Verilator simulations. Signed-off-by: Stefan Wallentowitz <stefan.wallentowitz@hm.edu>
This adds support for FuseSoC, currently for the verilator model only. Signed-off-by: Stefan Wallentowitz <stefan.wallentowitz@hm.edu>
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Thanks for getting the ball rolling on this @wallento. I've added a few minor comments, and have three big ones:
- A lot of the "tb" dirs/files in this repo are slated to be removed to encoruage people to use core-v-verif testbenches, so we'll need to replicate some of this there.
- tb/verilator-model/Makefile has a complete manifest embedded within it. This is exactly what we are trying to displace.
- Many (all?) of the RTL port map and parameter changes you suggest have been (or are being) taken care of elsewhere.
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Thanks, sorry, I have closed this one, because it was an accident (before testing). Will copy the comments over to the new one (#368) |
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Never be sorry for issuing a pull-request. We are pleased to have your contribution (even if we choose not to merge it in). |
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