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fpu: fmvp.d.x on RV32 with Q writes the register pair - #1962
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The register pair was selected only when FLEN = 2*XLEN, so on RV32 with
Q (FLEN = 128) fmvp.d.x fell through to fmv.w.x's path and wrote the
NaN-boxed low word: fmvp.d.x f10, x0, x11 gave 0xffffffff00000000
instead of {x11, 0}. The riscv-arch-test ZfaD-fmvp.d.x test shows it on
fdq_rv32gc and fdqh_rv32gc.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
This was referenced Oct 10, 2026
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On RV32 with Q (FLEN = 128),
fmvp.d.xfell through tofmv.w.x's path, because the register pair was selected only when FLEN = 2*XLEN:fmvp.d.x f10, x0, x11wrote the NaN-boxed low word, 0xffffffff00000000, instead of {x11, 0}. It now writes the pair, NaN-boxed to FLEN. The riscv-arch-testZfaD-fmvp.d.xtest shows the bug on fdq_rv32gc and fdqh_rv32gc, which the nightly regression runs again in the companion nightly PR.🤖 Generated with Claude Code