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Add a cycle-accounting performance monitor and sweep tools - #1960

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davidharrishmc wants to merge 3 commits into
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davidharrishmc:dh/perfmon
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openhwfoundation:mainfrom
davidharrishmc:dh/perfmon

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Adds an optional testbench performance monitor (wsim --params PERF_MONITOR=1, off by default) that charges every non-retiring cycle of each ELF to one cause, using LSU/IFU stall subcauses, traps, WFI, and a shadow tag pipeline for bubble causes (mispredicts, CSR writes, fences, load-use, MDU, divide). It also records cache fills and stall episodes, finds structural stalls without a true integer dependency, and samples the HPM events over the same window. bin/perfsweep runs the arch-test ELF directories (plus CoreMark and Embench with -b) through it, and bin/perfanalyze.py checks the accounting, cross-checks the HPM counters, and ranks lost cycles by cause and site, so stalls that point to RTL defects stand out. On rv64gc and rv32gc, every cycle of all 2,426 arch-test and benchmark ELFs is accounted for. The sweep found that the D$ miss counter also counts D$ flushes and CMOs (fix in a separate PR) and that MatchDE stalls on register fields the decode-stage instruction does not read.

🤖 Generated with Claude Code

testbench/common/perfmon.sv (enabled with wsim --params PERF_MONITOR=1) charges
every non-retiring cycle of each ELF to one cause: LSU or IFU stall
subcause, trap, WFI, or the bubble cause carried down a shadow tag pipeline
(mispredict, CSR write, fence, load-use, MDU, divide, ...).  It also records
stall episodes, cache fills, structural stalls without a true integer
dependency, and the HPM events over the same window, and writes per-ELF and
per-PC CSVs plus PERFANOM lines for anything it cannot explain.

bin/perfsweep runs the arch-test ELF directories (and optionally CoreMark and
Embench) with the monitor; bin/perfanalyze.py checks the accounting,
cross-checks the HPM counters, and reports lost cycles by cause and site.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
davidharrishmc and others added 2 commits October 10, 2026 12:20
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
…stall cause is active

An integer instruction whose rs field matches an FP load's rd usually also has
a real FP dependency on it (FPUStallD), so the bubble was not avoidable.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
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