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initial vector float reduction implementation - #1947

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zssmgosh wants to merge 13 commits into
openhwfoundation:vectorfrom
zssmgosh:vector
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zssmgosh wants to merge 13 commits into
openhwfoundation:vectorfrom
zssmgosh:vector

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@zssmgosh

@zssmgosh zssmgosh commented Oct 8, 2026

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vector reduction before testing

@georgiatai georgiatai left a comment

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some comments and reminder.
This file should be a module for a single lane in the VF execution unit

Comment thread src/vpu/fpeu/vfred.sv

logic [4:0] VfmaFlg;
logic [P.FLEN-1:0] VfmaRes;
postprocess #(P, 1) postproc (

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compact the signals to about 80 characters per line

Comment thread src/vpu/fpeu/vfred.sv
input logic [2:0] OpCtrlM,
input logic [P.FMALEN-1:0] SmM,
input logic [P.NE+1:0] SeM,
input logic AsM,

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some of these can be merged into one line, e.g. AsM, PsM,SsM, and the inf/nan/snan above

Comment thread src/vpu/fpeu/vfred.sv
logic ZZero;

unpackinput #(P) unpackX (
.A(X), .Fmt(FmaXFmt), .En(1'b1), .FPUActive,

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reminder that you would want 3 unpack in a lane. fma can take 3 operands

Comment thread src/vpu/fpeu/vfred.sv
output logic [P.NE+1:0] SeE,
output logic AsE,
output logic PsE,
output logic SsE,

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the final output should probably be a single EEW, post-processed element?

Comment thread src/vpu/fpeu/vfred.sv
////////////////////////////////////////////////////////////////////////////////////////////////

module vfred import cvw::*; #(parameter cvw_t P) (
input logic [P.FLEN-1:0] X, Z, // two operands

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These should probably be ELEN. refer to the block diagram

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2 participants