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[HIP] Enable support for USM memory pools #1689

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[HIP] Enable support for USM memory pools #1689

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014d08e
[HIP] Enable support for USM memory pools in HIP 6+
frasercrmck May 30, 2024
f70b05d
test gh
frasercrmck Jun 13, 2024
256074f
debug
frasercrmck Jun 13, 2024
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4 changes: 3 additions & 1 deletion .github/workflows/build-hw-reusable.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,9 @@ jobs:

- name: Test adapters
working-directory: ${{github.workspace}}/build
run: env UR_CTS_ADAPTER_PLATFORM="${{matrix.adapter.platform}}" ctest -C ${{matrix.build_type}} --output-on-failure -L "conformance" --timeout 180
run: |
${{ matrix.adapter.name == 'HIP' && 'env AMD_LOG_LEVEL=4 ./bin/test-enqueue --gtest_filter="urEnqueueKernelLaunchUSMLinkedList*" || echo fail' || '' }}
env UR_CTS_ADAPTER_PLATFORM="${{matrix.adapter.platform}}" ctest -C ${{matrix.build_type}} --output-on-failure -L "conformance" --timeout 180

- name: Get information about platform
if: ${{ always() }}
Expand Down
6 changes: 6 additions & 0 deletions source/adapters/hip/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,12 @@ if(NOT MSVC)
)
endif()

if(UMF_ENABLE_POOL_TRACKING)
target_compile_definitions(ur_adapter_hip PRIVATE UMF_ENABLE_POOL_TRACKING)
else()
message(WARNING "HIP adapter USM pools are disabled, set UMF_ENABLE_POOL_TRACKING to enable them")
endif()

set_target_properties(${TARGET_NAME} PROPERTIES
VERSION "${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}"
SOVERSION "${PROJECT_VERSION_MAJOR}"
Expand Down
19 changes: 15 additions & 4 deletions source/adapters/hip/usm.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -323,15 +323,25 @@ ur_result_t USMHostMemoryProvider::allocateImpl(void **ResultPtr, size_t Size,
ur_usm_pool_handle_t_::ur_usm_pool_handle_t_(ur_context_handle_t Context,
ur_usm_pool_desc_t *PoolDesc)
: Context(Context) {
if (PoolDesc) {
if (auto *Limits = find_stype_node<ur_usm_pool_limits_desc_t>(PoolDesc)) {
assert(PoolDesc);
const void *pNext = PoolDesc->pNext;
while (pNext != nullptr) {
const ur_base_desc_t *BaseDesc = static_cast<const ur_base_desc_t *>(pNext);
switch (BaseDesc->stype) {
case UR_STRUCTURE_TYPE_USM_POOL_LIMITS_DESC: {
const ur_usm_pool_limits_desc_t *Limits =
reinterpret_cast<const ur_usm_pool_limits_desc_t *>(BaseDesc);
for (auto &config : DisjointPoolConfigs.Configs) {
config.MaxPoolableSize = Limits->maxPoolableSize;
config.SlabMinSize = Limits->minDriverAllocSize;
}
} else {
break;
}
default: {
throw UsmAllocationException(UR_RESULT_ERROR_INVALID_ARGUMENT);
}
}
pNext = BaseDesc->pNext;
}

auto MemProvider =
Expand Down Expand Up @@ -379,7 +389,8 @@ UR_APIEXPORT ur_result_t UR_APICALL urUSMPoolCreate(
ur_usm_pool_handle_t *Pool ///< [out] pointer to USM memory pool
) {
// Without pool tracking we can't free pool allocations.
#ifdef UMF_ENABLE_POOL_TRACKING
#if defined(UMF_ENABLE_POOL_TRACKING) && HIP_VERSION_MAJOR >= 6
assert(PoolDesc);
if (PoolDesc->flags & UR_USM_POOL_FLAG_ZERO_INITIALIZE_BLOCK) {
return UR_RESULT_ERROR_UNSUPPORTED_FEATURE;
}
Expand Down
11 changes: 11 additions & 0 deletions test/conformance/enqueue/urEnqueueKernelLaunch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -497,31 +497,42 @@ TEST_P(urEnqueueKernelLaunchUSMLinkedList, Success) {
}

// Build linked list with USM allocations
printf("alloc head\n");
ASSERT_SUCCESS(urUSMSharedAlloc(context, device, nullptr, pool,
sizeof(Node),
reinterpret_cast<void **>(&list_head)));
printf("alloc head -> success (%p)\n", (void *)list_head);
ASSERT_NE(list_head, nullptr);
Node *list_cur = list_head;
for (int i = 0; i < num_nodes; i++) {
printf("loop iter %d\n", i);
list_cur->num = i * 2;
if (i < num_nodes - 1) {
printf("alloc next\n");
ASSERT_SUCCESS(
urUSMSharedAlloc(context, device, nullptr, pool, sizeof(Node),
reinterpret_cast<void **>(&list_cur->next)));
printf("alloc next -> success (%p)\n", (void*)list_cur->next);
ASSERT_NE(list_cur->next, nullptr);
} else {
list_cur->next = nullptr;
}
printf("update next %p -> %p\n", (void *)list_cur, (void *)list_cur->next);
list_cur = list_cur->next;
}
printf("loop done\n");

// Run kernel which will iterate the list and modify the values
printf("set arg\n");
ASSERT_SUCCESS(urKernelSetArgPointer(kernel, 0, nullptr, &list_head));
printf("enqueue kernel\n");
ASSERT_SUCCESS(urEnqueueKernelLaunch(queue, kernel, 1, &global_offset,
&global_size, nullptr, 0, nullptr,
nullptr));
printf("queue finish\n");
ASSERT_SUCCESS(urQueueFinish(queue));

printf("verify\n");
// Verify values
list_cur = list_head;
for (int i = 0; i < num_nodes; i++) {
Expand Down
167 changes: 90 additions & 77 deletions test/conformance/usm/usm_adapter_hip.match
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Original file line number Diff line number Diff line change
@@ -1,84 +1,97 @@
urUSMDeviceAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidNullPtrResult/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
# These pass on HIP 6.0+ but fails (unsupported) before then
{{OPT}}urUSMDeviceAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.InvalidNullPtrResult/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
urUSMDeviceAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_POOL
urUSMHostAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

# These pass on HIP 6.0+ but fails (unsupported) before then
{{OPT}}urUSMDeviceAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
{{OPT}}urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
{{OPT}}urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_POOL
{{OPT}}urUSMHostAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
urUSMPoolCreateTest.Success/AMD_HIP_BACKEND___{{.*}}_

# These pass on HIP 6.0+ but fails (unsupported) before then
{{OPT}}urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
{{OPT}}urUSMPoolCreateTest.Success/AMD_HIP_BACKEND___{{.*}}_

urUSMPoolCreateTest.SuccessWithFlag/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_CONTEXT
urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_REFERENCE_COUNT
urUSMPoolGetInfoTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidEnumerationProperty/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidSizeZero/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidSizeTooSmall/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidNullPointerPropValue/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidNullPointerPropSizeRet/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolDestroyTest.Success/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolDestroyTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolRetainTest.Success/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolRetainTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
urUSMSharedAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.SuccessWithMultipleAdvices/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

# These pass on HIP 6.0+ but fails (unsupported) before then
{{OPT}}urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_CONTEXT
{{OPT}}urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_REFERENCE_COUNT
{{OPT}}urUSMPoolGetInfoTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidEnumerationProperty/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidSizeZero/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidSizeTooSmall/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidNullPointerPropValue/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidNullPointerPropSizeRet/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolDestroyTest.Success/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolDestroyTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolRetainTest.Success/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolRetainTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMSharedAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.SuccessWithMultipleAdvices/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048

# These pass on HIP 6.0+ but fails (unsupported) before then
{{OPT}}urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
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