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[HIP] Enable support for USM memory pools
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Copies code for the pool descriptor from the CUDA adapter.

Fixes #1479.
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@frasercrmck
frasercrmck committed May 30, 2024
1 parent 7a6622f commit fbaf222
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Showing 3 changed files with 18 additions and 80 deletions.
6 changes: 6 additions & 0 deletions source/adapters/hip/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -93,6 +93,12 @@ if(NOT MSVC)
)
endif()

if(UMF_ENABLE_POOL_TRACKING)
target_compile_definitions(ur_adapter_hip PRIVATE UMF_ENABLE_POOL_TRACKING)
else()
message(WARNING "HIP adapter USM pools are disabled, set UMF_ENABLE_POOL_TRACKING to enable them")
endif()

set_target_properties(${TARGET_NAME} PROPERTIES
VERSION "${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}"
SOVERSION "${PROJECT_VERSION_MAJOR}"
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15 changes: 12 additions & 3 deletions source/adapters/hip/usm.cpp
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Expand Up @@ -327,15 +327,24 @@ ur_result_t USMHostMemoryProvider::allocateImpl(void **ResultPtr, size_t Size,
ur_usm_pool_handle_t_::ur_usm_pool_handle_t_(ur_context_handle_t Context,
ur_usm_pool_desc_t *PoolDesc)
: Context(Context) {
if (PoolDesc) {
if (auto *Limits = find_stype_node<ur_usm_pool_limits_desc_t>(PoolDesc)) {
const void *pNext = PoolDesc->pNext;
while (pNext != nullptr) {
const ur_base_desc_t *BaseDesc = static_cast<const ur_base_desc_t *>(pNext);
switch (BaseDesc->stype) {
case UR_STRUCTURE_TYPE_USM_POOL_LIMITS_DESC: {
const ur_usm_pool_limits_desc_t *Limits =
reinterpret_cast<const ur_usm_pool_limits_desc_t *>(BaseDesc);
for (auto &config : DisjointPoolConfigs.Configs) {
config.MaxPoolableSize = Limits->maxPoolableSize;
config.SlabMinSize = Limits->minDriverAllocSize;
}
} else {
break;
}
default: {
throw UsmAllocationException(UR_RESULT_ERROR_INVALID_ARGUMENT);
}
}
pNext = BaseDesc->pNext;
}

auto MemProvider =
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77 changes: 0 additions & 77 deletions test/conformance/usm/usm_adapter_hip.match
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@@ -1,86 +1,9 @@
urUSMDeviceAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidNullPtrResult/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
urUSMDeviceAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
urUSMDeviceAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_BASE_PTR
urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_SIZE
urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_POOL
urUSMHostAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
urUSMPoolCreateTest.Success/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolCreateTest.SuccessWithFlag/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_CONTEXT
urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_REFERENCE_COUNT
urUSMPoolGetInfoTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidEnumerationProperty/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidSizeZero/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidSizeTooSmall/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidNullPointerPropValue/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolGetInfoTest.InvalidNullPointerPropSizeRet/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolDestroyTest.Success/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolDestroyTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolRetainTest.Success/AMD_HIP_BACKEND___{{.*}}_
urUSMPoolRetainTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
urUSMSharedAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.SuccessWithMultipleAdvices/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048

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