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opt everything
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@frasercrmck
frasercrmck committed Jun 11, 2024
1 parent 492f56d commit e05c55e
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2 changes: 2 additions & 0 deletions test/conformance/enqueue/enqueue_adapter_hip.match
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{{OPT}}urEnqueueKernelLaunchTest.InvalidKernelArgs/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urEnqueueKernelLaunchKernelWgSizeTest.NonMatchingLocalSize/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urEnqueueKernelLaunchKernelSubGroupTest.Success/AMD_HIP_BACKEND___{{.*}}_
# This passes on HIP 6.0+ but fails (unsupported) before then
{{OPT}}urEnqueueKernelLaunchUSMLinkedList.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urEnqueueMemBufferCopyRectTestWithParam.Success/AMD_HIP_BACKEND___{{.*}}___copy_row_2D
{{OPT}}urEnqueueMemBufferCopyRectTestWithParam.Success/AMD_HIP_BACKEND___{{.*}}___copy_3d_2d
{{OPT}}urEnqueueMemBufferFillTest.Success/AMD_HIP_BACKEND___{{.*}}___size__256__patternSize__256
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75 changes: 75 additions & 0 deletions test/conformance/usm/usm_adapter_hip.match
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# Passes and fails
{{OPT}}urUSMDeviceAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.InvalidNullPtrResult/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

{{OPT}}urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMDeviceAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled
{{OPT}}urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_BASE_PTR

# Passes and fails
{{OPT}}urUSMGetMemAllocInfoTest.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_ALLOC_INFO_POOL
{{OPT}}urUSMHostAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

{{OPT}}urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled

# Passes and fails
{{OPT}}urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048
{{OPT}}urUSMPoolCreateTest.Success/AMD_HIP_BACKEND___{{.*}}_

{{OPT}}urUSMPoolCreateTest.SuccessWithFlag/AMD_HIP_BACKEND___{{.*}}_

# Passes and fails
{{OPT}}urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_CONTEXT
{{OPT}}urUSMPoolGetInfoTestWithInfoParam.Success/AMD_HIP_BACKEND___{{.*}}___UR_USM_POOL_INFO_REFERENCE_COUNT
{{OPT}}urUSMPoolGetInfoTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidEnumerationProperty/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidSizeZero/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidSizeTooSmall/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidNullPointerPropValue/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolGetInfoTest.InvalidNullPointerPropSizeRet/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolDestroyTest.Success/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolDestroyTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolRetainTest.Success/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMPoolRetainTest.InvalidNullHandlePool/AMD_HIP_BACKEND___{{.*}}_
{{OPT}}urUSMSharedAllocTest.Success/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.SuccessWithDescriptors/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.SuccessWithMultipleAdvices/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.InvalidNullHandleDevice/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.InvalidNullPtrMem/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled

{{OPT}}urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled

# Passes and fails
{{OPT}}urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512
{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048

{{OPT}}{{Segmentation fault|Aborted}}

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