Fp32 abcd bf16 a bcd16b reorder #956
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Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Fixed offsets for gemm_blas convolution Fixed offsets for pooling Fixed gemm deconvolution for batch more than 1 with custom strides NCDHW Deconvolution with concat issue fix compute offset for conv + concat
Primimitives that supports new post ops: - Jit Convolutions (FP32,INT8) - Jit,Ref Pooling (INT8)
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Allow to set data handler without padding processing. Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
…in output tensors
There is a problem with compilation with -wundef warning flag. Include tbb directory by --system alow to avoid checker passes for TBB headers.
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
Signed-off-by: Alexander Peskov <alexander.peskov@intel.com>
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FP32_abcd_BF16_aBcd16b reorder was enabled: addedto cpu_reorder list and changed is_applicable conditions to mb_stride_relaxed_match