Fix jsons

DirectProgramming/C++SYCL_FPGA/README.md

@@ -56,7 +56,8 @@ flowchart LR
 |:---                                                       |:---                                                  |:---
 | [fpga_compile](Tutorials/GettingStarted/fpga_compile)     | [Tutorials/GettingStarted](Tutorials/GettingStarted) | How and why compiling SYCL* code for FPGA differs from CPU or GPU <br> FPGA device image types and when to use them. <br> The compile options used to target FPGA
 | [fast_recompile](Tutorials/GettingStarted/fast_recompile) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | Why to separate host and device code compilation in your FPGA project <br> How to use the `-reuse-exe` and device link. <br> Which method to choose for your project
-| [fpga_template](Tutorials/GettingStarted/fpga_template) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | Showcases the CMake build system that is used in other code samples, and serves as a template that you can re-use in your own designs.
+| [fpga_template](Tutorials/GettingStarted/fpga_template) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | An Intel® FPGA tutorial that explains the CMake build system that is used in other code samples, and serves as a template that you can re-use in your own designs
+[component_interfaces_comparison](Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison)                 | [Tutorials/Features/hls_flow_interfaces](Tutorials/Features/hls_flow_interfaces) | This sample introduces different invocation/data interfaces that can be used for IP components
 
 #### Tier 2: Explore the Fundamentals
 
@@ -80,7 +81,6 @@ flowchart LR
 |:---                                                                                                                           |:---                                                                                      |:---
 | [ac_fixed](Tutorials/Features/ac_fixed)                                                                                       | [Tutorials/Features](Tutorials/Features)                                                 | How different methods of `ac_fixed` number construction affect hardware resource utilization <br> Recommended method for constructing `ac_fixed` numbers in your kernel <br> Accessing and using the `ac_fixed` math library functions <br> Trading off accuracy of results for reduced resource usage on the FPGA
 | [ac_int](Tutorials/Features/ac_int)                                                                                           | [Tutorials/Features](Tutorials/Features)                                                 | Using the `ac_int` data type for basic operations <br> Efficiently using the left shift operation <br> Setting and reading certain bits of an `ac_int` number
-| [component_interfaces_comparison](Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison)                 | [Tutorials/Features/hls_flow_interfaces](Tutorials/Features/hls_flow_interfaces) | This sample introduces different invocation/data interfaces that can be used when creating FPGA IP with the Intel® oneAPI DPC++/C++ Compiler
 | [device_global (experimental)](Tutorials/Features/experimental/device_global)                                                 | [Tutorials/Features](Tutorials/Features)                                                 | The basic usage of the `device_global` class <br> How to initialize a `device_global` to non-zero values
 | [double_buffering](Tutorials/DesignPatterns/double_buffering)                                                                 | [Tutorials/DesignPatterns](Tutorials/DesignPatterns)                                     | How and when to implement the double buffering optimization technique
 | [explicit_data_movement](Tutorials/DesignPatterns/explicit_data_movement)                                                     | [Tutorials/DesignPatterns](Tutorials/DesignPatterns)                                     | How to explicitly manage the movement of data for the FPGA

DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/README.md

@@ -1,4 +1,4 @@
-# Component Interfaces Overview
+# Component Interfaces Comparison
 This sample introduces different invocation/data interfaces that can be used when creating FPGA IP with the Intel® oneAPI DPC++/C++ Compiler.
 
 | Area                 | Description
@@ -26,8 +26,7 @@ This sample introduces different invocation/data interfaces that can be used whe
 
 > **Warning**: Make sure you add the device files associated with the FPGA that you are targeting to your Intel® Quartus® Prime installation.
 
-This sample is part of the FPGA code samples. It is categorized as a Tier 2 sample that demonstrates compiler features.
-
+This sample is part of the FPGA code samples. It is categorized as a Tier 1 sample that helps you getting started.
 ```mermaid
 flowchart LR
    tier1("Tier 1: Get Started")
@@ -37,8 +36,8 @@ flowchart LR
 
    tier1 --> tier2 --> tier3 --> tier4
 
-   style tier1 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
-   style tier2 fill:#f96,stroke:#333,stroke-width:1px,color:#fff
+   style tier1 fill:#f96,stroke:#333,stroke-width:1px,color:#fff
+   style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
    style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
    style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
 ```

DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/sample.json

@@ -1,8 +1,8 @@
 {
     "guid": "7d8482f5-39f1-4cf1-aa2e-a1f72cfc47cb",
-    "name": "SYCL HLS Flow Interfaces Overview",
-    "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Features"],
-    "description": "Intel® FPGA example designs oversewing different interfaces for the SYCL HLS flow",
+    "name": "Component Interfaces Comparison",
+    "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Getting Started Tutorials"],
+    "description": "Intel® FPGA tutorial introducing different invocation/data interfaces that can be used for IP components",
     "toolchain": ["icpx"],
     "os": ["linux", "windows"],
     "targetDevice": ["FPGA"],

DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/invocation_interfaces/sample.json

@@ -1,8 +1,8 @@
 {
   "guid": "69415BED-D452-449A-8F5A-DB01ACCE38DC",
   "name": "Invocation Interfaces",
-  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Features/hls_flow_interfaces"],
-  "description": "An Intel® FPGA tutorial demonstrating the usage of register_map and streaming invocation interfaces",
+  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Features/HLS Flow: Interfaces"],
+  "description": "An Intel® FPGA tutorial that demonstrates the differences between a streaming invocation interface and a register-mapped invocation interface on an IP component",
   "toolchain": ["icpx"],
   "os": ["linux", "windows"],
   "targetDevice": ["FPGA"],

DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/mmhost/sample.json

@@ -1,8 +1,8 @@
 {
   "guid": "CE509751-B84A-44D1-A391-2007937F3A7F",
   "name": "Avalon Memory-Mapped Host Interfaces",
-  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Features/hls_flow_interfaces"],
-  "description": "An Intel® FPGA tutorial demonstrating how to use annotated pointers to customize Avalon memory-mapped host interfaces",
+  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Features/HLS FLow: Interfaces"],
+  "description": "An Intel® FPGA tutorial demonstrating how to annotate pointer arguments to customize Avalon memory-mapped host interfaces",
   "toolchain": ["icpx"],
   "os": ["linux", "windows"],
   "targetDevice": ["FPGA"],

DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/streaming_data_interfaces/sample.json

@@ -1,7 +1,7 @@
 {
   "guid": "aeaca2ce-126e-452b-a6e3-2a3d5b1dbf55",
-  "name": "Streaming Interfaces",
-  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/hls_flow_interfaces/streaming_data_interfaces"],
+  "name": "Streaming Data Interfaces",
+  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/HLS Flow: Interfaces"],
   "description": "An Intel® FPGA tutorial demonstrating how to use pipes to implement streaming interfaces on IP Components",
   "toolchain": ["icpx"],
   "os": ["linux", "windows"],

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/sample.json

@@ -2,7 +2,7 @@
   "guid": "A211FDE2-B037-4069-BD84-C45E354798B7",
   "name": "FPGA Compile",
   "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Getting Started Tutorials"],
-  "description": "Intel® FPGA tutorial introducing how to SYCL for Intel® FPGA",
+  "description": "Intel® FPGA tutorial introducing how to use SYCL to target FPGAs",
   "toolchain": ["icpx"],
   "os": ["linux", "windows"],
   "targetDevice": ["FPGA"],

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/sample.json

@@ -2,7 +2,7 @@
   "guid": "418AA4D8-0A61-4FDB-845A-CDA4DA0655E7",
   "name": "FPGA Template",
   "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Getting Started Tutorials"],
-  "description": "This project serves as a template for Intel® oneAPI DPC++/C++ designs targeting FPGAs. ",
+  "description": "An Intel® FPGA tutorial that explains the CMake build system that is used in other code samples, and serves as a template that you can re-use in your own designs",
   "toolchain": ["icpx"],
   "os": ["linux", "windows"],
   "targetDevice": ["FPGA"],

DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/platform_designer/sample.json

@@ -1,7 +1,7 @@
 {
   "guid": "293B78FB-40A3-4F81-A3CB-D2C3ED344AE1",
   "name": "Platform Designer - Intel® Arria® 10 SX SoC Developer Kit",
-  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Tools/experimental"],
+  "categories": ["Toolkit/oneAPI Direct Programming/C++SYCL FPGA/Tutorials/Tools"],
   "description": "An Intel® FPGA tutorial demonstrating how to export a reusable IP component to Intel® Quartus® Prime Pro and Platform Designer.",
   "toolchain": ["icpx"],
   "os": ["linux", "windows"],