Skip to content

FPGA: New Code Sample minimum_latency #1302

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 7 commits into from
Feb 8, 2023
+677 −0
Merged

FPGA: New Code Sample minimum_latency #1302

Changes from 1 commit
Commits
Show all changes
7 commits
Select commit Hold shift + click to select a range
02b9fc0
Introduce the code sample
shuoniu-intel Jan 6, 2023
54a43ec
Update the design and add a new target manual_revert
shuoniu-intel Jan 9, 2023
18d3609
Create README
shuoniu-intel Jan 16, 2023
c8cdfa0
Address Yohann's comments
shuoniu-intel Jan 18, 2023
ef74d46
Update directory path in README
shuoniu-intel Jan 19, 2023
d2d1344
Incorporate a global change
shuoniu-intel Jan 30, 2023
e98e5bd
Address John's comments
shuoniu-intel Feb 1, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
Update directory path in README
  • Loading branch information
@shuoniu-intel
shuoniu-intel committed Jan 19, 2023
commit ef74d46be50a6b80618a600842c33b664e78595f
4 changes: 2 additions & 2 deletions ...g/C++SYCL_FPGA/Tutorials/Features/optimization_levels/minimum_latency/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,8 @@ flowchart LR
style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
```

Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/DPC++FPGA/README.md).
You can also find more information about [troubleshooting build errors](/DirectProgramming/DPC++FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/DPC++FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/DPC++FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/DPC++FPGA/README.md#documentation), etc.
Find more information about how to navigate this part of the code samples in the [FPGA top-level README.md](/DirectProgramming/C++SYCL_FPGA/README.md).
You can also find more information about [troubleshooting build errors](/DirectProgramming/C++SYCL_FPGA/README.md#troubleshooting), [running the sample on the Intel® DevCloud](/DirectProgramming/C++SYCL_FPGA/README.md#build-and-run-the-samples-on-intel-devcloud-optional), [using Visual Studio Code with the code samples](/DirectProgramming/C++SYCL_FPGA/README.md#use-visual-studio-code-vs-code-optional), [links to selected documentation](/DirectProgramming/C++SYCL_FPGA/README.md#documentation), etc.

## Purpose

Expand Down