Invalid byte select during instruction fetches on the Servile wishbone bus

[deliciouslytyped]

I'm very new to all of this, but I seem to be running into the issue stemming from the Servile wishbone data bus not having a way to differentiate between instruction fetches and data fetches.

Specifically, byte select seems to be invalid during instruction fetches, but there is no way to tell that this is the case and so force a full 4 byte word read.

My problem is thus that if I use the byte select unconditionally, it ends up being set to 1 for instruction fetches, and I end up immediately fetching instructions incorrectly.

Instruction fetches seem to require the full 4 byte data word (regardless of the byte select setting), while data fetches do use the wishbone byte select correctly.

This seems like a pretty important oversight, so I'm sure I'm missing something.

[olofk]

You're right. the byte select signal (o_wb_mem_sel) is incorrect for instruction fetches. servile assumes that all reads are 32-bit wide. In practice this tends to work anyway since the sel signal is ignored by most memories during reads and we get a 32-bit word back regardless of what sel is set to.

[deliciouslytyped]

I seem to have edited out my mention of the issue - that the reason this is a problem for me is that the size of r/w matters for memory ranges of MMIO devices - where in this case the MMIO is handled by the "memory"-side of the bus, not the CPU.

[deliciouslytyped]

Unrelated, thanks for all the tooling getting started stuff: fusesoc, the verilator harness, the zephyr/west sample code, etc. and the readmes have all been an excellent help!