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Fixes #423 by making the Vivado project a normal dependency of the other targets to ensure synthesis and implementation are rerun if a source file is updated.

@craigjb
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craigjb commented Jan 2, 2026

I'm also interested in this PR for FuseSoC. It seems like changes to verilog source files aren't triggering a build. I have to pass --clean to fusesoc run ... every time. The source file in this case is coming from a generator (not cached).

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Vivado flow not re-run when Verilog parameter is changed

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