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Port Comballoc
to work on CFG values
#2163
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I am slightly concerned about modifying instruction description in place without chaning instruction ids. It is currently safe (e.g., liveness is not yet precomputed, we only replace Alloc with a pure instruction not introducing enew ffects), but may lead to tricky bugs due to e.g., caching based on instruction ids or instructions themselves. Do we do it in other places?
Possible future improvement: when allocations of different modes are interleaved within a block, they can be combined into just two allocations (one of each mode), for example: H1;L1;H2;L2
would be combined into H12;L12
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I have tested the code a bit more, and |
On the compiler code, both pipeline |
This pull request, as the title suggests,
is merely a port of the
Comballoc
optimization pass to CFG values.
However, the code is significantly
different, taking advantage of the
representation of basic blocks and
the ability to change / insert
instructions quite easily.
Since this code has a lot of potential
in terms of miscompilation, we should
not merge it before further testing.