128-bit SIMD vector primitive type

.github/CODEOWNERS

@@ -76,3 +76,6 @@ testsuite/flambda2-test-list    @xclerc
 tools/merge_archives.ml         @mshinwell @xclerc
 tools/merge_dot_a_files.sh      @mshinwell @xclerc
 tools/objinfo.ml                @mshinwell @xclerc
+
+testsuite/tests/unboxed-primitive-args  @TheNumbat
+tests/simd                              @TheNumbat

backend/CSEgen.ml

@@ -233,7 +233,7 @@ class cse_generic = object (self)
 method class_of_operation op =
   match op with
   | Imove | Ispill | Ireload -> assert false   (* treated specially *)
-  | Iconst_int _ | Iconst_float _ | Iconst_symbol _ -> Op_pure
+  | Iconst_int _ | Iconst_float _ | Iconst_symbol _ | Iconst_vec128 _ -> Op_pure
   | Icall_ind | Icall_imm _ | Itailcall_ind | Itailcall_imm _
   | Iextcall _ | Iprobe _ | Iopaque -> assert false  (* treated specially *)
   | Istackoffset _ -> Op_other

backend/afl_instrument.ml

@@ -93,7 +93,7 @@ and instrument = function
   | Ctail e -> Ctail (instrument e)
 
   (* these are base cases and have no logging *)
-  | Cconst_int _ | Cconst_natint _ | Cconst_float _
+  | Cconst_int _ | Cconst_natint _ | Cconst_float _ | Cconst_vec128 _
   | Cconst_symbol _
   | Cvar _ as c -> c
 

backend/amd64/CSE.ml

@@ -45,7 +45,7 @@ method! class_of_operation op =
   | Icompf _
   | Icsel _
   | Ifloatofint | Iintoffloat | Ivalueofint | Iintofvalue
-  | Iconst_int _ | Iconst_float _ | Iconst_symbol _
+  | Iconst_int _ | Iconst_float _ | Iconst_symbol _ | Iconst_vec128 _
   | Icall_ind | Icall_imm _ | Itailcall_ind | Itailcall_imm _ | Iextcall _
   | Istackoffset _ | Iload _ | Istore _ | Ialloc _
   | Iintop _ | Iintop_imm _ | Iintop_atomic _

backend/amd64/arch.ml

@@ -31,6 +31,9 @@ let prefetchwt1_support = ref false
 (* Emit elf notes with trap handling information. *)
 let trap_notes = ref true
 
+(* Enables usage of vector registers. *)
+let simd_regalloc_support = ref false
+
 (* Machine-specific command-line options *)
 
 let command_line_options =
@@ -59,6 +62,10 @@ let command_line_options =
       " Emit .note.ocaml_eh section with trap handling information (default)";
     "-fno-trap-notes", Arg.Clear trap_notes,
       " Do not emit .note.ocaml_eh section with trap handling information";
+    "-fsimd", Arg.Set simd_regalloc_support,
+      " Enable register allocation for SIMD vectors";
+    "-fno-simd", Arg.Clear simd_regalloc_support,
+      " Disable register allocation for SIMD vectors (default)"
   ]
 
 (* Specific operations for the AMD64 processor *)
@@ -130,6 +137,8 @@ let size_addr = 8
 let size_int = 8
 let size_float = 8
 
+let size_vec128 = 16
+
 let allow_unaligned_access = true
 
 (* Behavior of division *)