CAD for VLSI assignments

Assignment 1 : Parameterized Carry Ripple Adder and Carry Lookahead Adder

The objectives of this assignment are:

• To create a C++ code that generates a Carry Ripple Adder and a Carry Lookahead Adder in Verilog.
• To compare the power, area, timing of both the adders.

Assignment 2 : Parameterized Pipelined Wallace Tree Multiplier

The objectives of this assignment is:

• To write a C++ code that generates a Parameterized Pipelined Wallace tree multiplier
• To study the effects of pipelining on Latency, throughput and area.