Electrical Engineering @ IIT Delhi — Dept. Rank 1. Research in quantum computing. Incoming Software Engineering Intern @ Virtu Financial, Summer 2027.
Previously a Research Intern in the Trusted Systems Group at CISPA Helmholtz Center, where I graded 131 open-source RISC-V CPU and GPU cores against their own security claims. Publication in progress.
Outside research I build low-latency systems — execution paths in C++, data planes in FPGA fabric, and the hardware underneath them.
namangoyal.me · Research · Projects · CV · LinkedIn
| fpga-tick-to-trade | Deterministic, formally verified tick-to-trade engine in FPGA fabric · SystemVerilog |
| fpga-net-parser | Wire-speed MAC/IP/UDP parser with a fixed-latency L1 trigger; verified with SymbiYosys + cocotb · SystemVerilog |
| unitary-decomposer | Solovay–Kitaev decomposition of SU(2) unitaries at O(log^2.71(1/ε)) · Python |
| KAN-PINN-Battery-SOH | Kolmogorov–Arnold + physics-informed network for lithium-ion state-of-health · PyTorch |
Focus: low-latency C++ · FPGA / SystemVerilog · quantum computing · algorithms · hardware security


