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Release v1.1.1:
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-Fixed bug in InjectionQ where flits were lost during saturation
-Added pipeline registers between routers to help better meet timing
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@ffard-lbl
ffard-lbl committed Jul 3, 2015
1 parent c2913c9 commit 1d711d0
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Showing 5 changed files with 49 additions and 16 deletions.
15 changes: 9 additions & 6 deletions src/main/scala/channelq.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -51,10 +51,12 @@ class InjectionQStateMgmt(parms: Parameters) extends Module(parms){
}.elsewhen(curState === injQState.xmit){
when(!io.creditsAvailable){
curState := injQState.hold
}.elsewhen(io.creditsAvailable && io.inputIsTail){
curState := injQState.idle
}.otherwise{
curState := injQState.xmit
when(io.inputIsTail) {
curState := injQState.idle
} .otherwise {
curState := injQState.xmit
}
}
}.elsewhen(curState === injQState.hold){
when(io.creditsAvailable){
Expand All @@ -76,6 +78,7 @@ class InjectionChannelQ(parms: Parameters) extends Module(parms) {

val queueDepth = parms.get[Int]("queueDepth")
val numVCs = parms.get[Int]("numVCs")
val credThreshold = parms.get[Int]("credThreshold")
val vcArbCtor = parms.get[Parameters=>Arbiter]("vcArbCtor")

val flitWidth : Int = io.in.flit.getWidth
Expand Down Expand Up @@ -121,18 +124,18 @@ class InjectionChannelQ(parms: Parameters) extends Module(parms) {
// --- State Machine Logic ---
injQStateMachine.io.inputBufferValid := queue.io.deq.valid
injQStateMachine.io.vcAllocGranted := vcArbiter.io.resource.valid
injQStateMachine.io.creditsAvailable := outCredits(chosen) // && ~almostOutCredits(chosen)
injQStateMachine.io.creditsAvailable := outCredits(chosen) && ~almostOutCredits(chosen)
injQStateMachine.io.inputIsTail := queue.io.deq.bits.isTail() && queue.io.deq.valid
// ------------------

// ---- DEBUG ---
assert(((queue.io.enq.ready && io.in.flitValid) || (~io.in.flitValid)), "InjQ " + parms.path.head + ": queue overflow")
// assert(((queue.io.enq.ready && io.in.flitValid) || (~io.in.flitValid)), "InjQ " + parms.path.head + ": queue overflow")
//----------


//--- Input Logic ---
queue.io.enq.bits <> io.in.flit
queue.io.enq.valid := io.in.flitValid
queue.io.enq.valid := (UInt(queueDepth) - queue.io.count) > UInt(credThreshold) && io.in.flitValid
creditGen.io.inGrant := queue.io.deq.ready && queue.io.deq.valid
creditGen.io.outCredit <> io.in.credit
//------------
Expand Down
6 changes: 3 additions & 3 deletions src/main/scala/credit.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,8 @@ class CreditGen(parms: Parameters) extends Module(parms) {
}

class CreditCon(parms: Parameters) extends Module(parms) {
val numCreds = parms.get[Int]("numCreds")
val numCreds = parms.get[Int]("numCreds")
val threshold = parms.get[Int]("credThreshold")
val io = new Bundle {
val inCredit = new Credit().flip()
val inConsume = Bool(INPUT)
Expand All @@ -41,8 +42,7 @@ class CreditCon(parms: Parameters) extends Module(parms) {
//val credCount = UInt(width = log2Up(numCreds)+1).asOutput
}
val credCount = Reg(init=UInt(numCreds, log2Up(numCreds)+1))
val threshold = 1


when (credCount === UInt(numCreds)) {
credCount := credCount - io.inConsume.toUInt()
} .elsewhen ((credCount > UInt(threshold))) {// && (credCount < UInt(numCreds))) {
Expand Down
13 changes: 8 additions & 5 deletions src/main/scala/main.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -298,7 +298,8 @@ object OpenSoC {
("TopologyDimension"->Hard(Dim)),
("RoutersPerDim"->Hard(K)),
("Concentration"->Hard(C)),
("numVCs"->Soft(numVCs)),
("numVCs"->Hard(numVCs)),
("credThreshold"->Hard(1)),

("queueDepth"->Soft(16)),

Expand All @@ -321,7 +322,8 @@ object OpenSoC {
("TopologyDimension"->Hard(Dim)),
("RoutersPerDim"->Hard(K)),
("Concentration"->Hard(C)),
("numVCs"->Soft(numVCs)),
("numVCs"->Hard(numVCs)),
("credThreshold"->Hard(1)),

("queueDepth"->Soft(16)),

Expand All @@ -334,7 +336,7 @@ object OpenSoC {
("destCordDim"->Hard(Dim + C)),

("flitIDWidth"->Hard(4)),
("payloadWidth"->Hard(4)),
("payloadWidth"->Hard(32)),
("breadCrumbCount"->Soft(1)),
("InputFlitizer"->Soft((parms: Parameters) => new FlitToFlit(parms)))
)
Expand Down Expand Up @@ -373,8 +375,9 @@ object OpenSoC {
("numResources"->Hard(numPortsCFlatBfly)),

("queueDepth"->Soft(16)),
("numVCs"->Soft(numVCs)),

("numVCs"->Hard(numVCs)),
("credThreshold"->Hard(1)),

("packetTypeWidth"->Hard(4)),
("packetMaxLength"->Hard(16)),
("packetWidth"->Hard(32)),
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/networkinterface.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ class InputPacketInterface[T <: Data](parms: Parameters, tGen : Parameters => T)

io.in.ready := packet2Flit.io.packetReady
packet2Flit.io.packet := io.in.bits
packet2Flit.io.packetValid := io.in.valid
packet2Flit.io.packetValid := io.in.valid

creditCon.io.inCredit <> io.out.credit
io.out.flit := packet2Flit.io.flit
Expand Down
29 changes: 28 additions & 1 deletion src/main/scala/topology.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,28 @@ import scala.runtime.ScalaRunTime._
// Topology Specific paramters are defined in child instantiations of this parameters class
}*/

class CreditBuffer(parms: Parameters) extends Module(parms){

val numVCs = parms.get[Int]("numVCs")

val io = new Bundle{
val in = new ChannelVC(parms)
val out = new ChannelVC(parms).flip()
}

io.out.flit := io.in.flit
io.out.flitValid := io.in.flitValid

for (c <- 0 until numVCs){
val creditDelay = Reg(init=UInt(0, width=1 ))
creditDelay := io.out.credit(c).grant
io.in.credit(c).grant := creditDelay
}

}



abstract class Topology(parms: Parameters) extends Module(parms) {
val Dim = parms.get[Int]("TopologyDimension") // Dimension of topology
val K = parms.get[Vector[Int]]("RoutersPerDim") // Routers per dimension.
Expand Down Expand Up @@ -128,6 +150,7 @@ class CMesh(parms: Parameters) extends Topology(parms) {
// println("numRouters: " + numRouters)
var connectionsMap = new HashMap[Vector[Int], Array[Int]]()
var busProbesMap = new HashMap[Vector[Int], BusProbe]()
var creditBufsMap = new HashMap[Vector[Int], CreditBuffer]()
for (n <- 0 until numRouters) {
// println("coord: " + coord)
var newRouter = Chisel.Module ( routerCtor(
Expand All @@ -142,9 +165,11 @@ class CMesh(parms: Parameters) extends Topology(parms) {
))))
//var newBusProbe = Chisel.Module( new BusProbe(parms) )
var newBusProbe = Chisel.Module( new BusProbe(parms.child("BusProbeParms", Map( ("routerRadix"->Soft(routerRadix)) )) ) )
var newcreditBuf = Chisel.Module( new CreditBuffer(parms))
routermap += coord -> newRouter
connectionsMap += coord -> Array.fill(routerRadix)(0)
busProbesMap += coord -> newBusProbe
creditBufsMap += coord -> newcreditBuf
// Create the channels. Channels are indexed by the coordinates of the router that is feeding them flits (they are output channels for the router), and an integer with the port number.
coord = IncrementCoord(coord)
}
Expand All @@ -158,7 +183,9 @@ class CMesh(parms: Parameters) extends Topology(parms) {
// This is the messy part. We need to connect the same channel to the router that has it as input. Depending on i, we have to fetch the router.
var consumerrouter = FindConsumerRouter(coord, i) // - C is contained here. The index refers to channels after the first C ones (the first indexed channels are I/E
if (consumerrouter != coord) { // If they are equal it means that there is no appropriate neighbor router.
routermap(consumerrouter).io.inChannels(i) <> routermap(coord).io.outChannels(i)
//routermap(consumerrouter).io.inChannels(i) <> routermap(coord).io.outChannels(i)
routermap(consumerrouter).io.inChannels(i) <> creditBufsMap(coord).io.out
creditBufsMap(coord).io.in <> routermap(coord).io.outChannels(i)
busProbesMap(coord).io.inFlit(i) := routermap(coord).io.outChannels(i).flit
busProbesMap(coord).io.inValid(i) := routermap(coord).io.outChannels(i).flitValid
busProbesMap(coord).io.routerCord := UInt(consumerrouter.product)
Expand Down

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