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This is an ASM program to implement a single-layer perceptron realization of logic gates.

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SLP-Ripes-RISCV

This is an ASM program implemented on RIPES to implement a single-layer perceptron realization of logic gates.

This project realizes AND, NOT and OR logic gates.

Further updates will include realization of non-linear classifiable gates - XOR and XNOR.

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This is an ASM program to implement a single-layer perceptron realization of logic gates.

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