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Floating-point extensions for RISC-V can specify rounding mode embedded in the instruction (like Intel's AVX-512). They could be faster than fesetround
.
The C code should be something like:
// float
asm("fadd.s %0, %1, %2, rne" : "=f"(result_ne) : "f"(x), "f"(y)); // roundTiesToEven
asm("fadd.s %0, %1, %2, rmm" : "=f"(result_away) : "f"(x), "f"(y)); // roundTiesToAway
asm("fadd.s %0, %1, %2, rup" : "=f"(result_up) : "f"(x), "f"(y)); // roundTowardPositive
asm("fadd.s %0, %1, %2, rdn" : "=f"(result_down) : "f"(x), "f"(y)); // roundTowardNegative
asm("fadd.s %0, %1, %2, rtz" : "=f"(result_zero) : "f"(x), "f"(y)); // roundTowardZero
// double
asm("fadd.d %0, %1, %2, rne" : "=f"(result_ne) : "f"(x), "f"(y)); // roundTiesToEven
asm("fadd.d %0, %1, %2, rmm" : "=f"(result_away) : "f"(x), "f"(y)); // roundTiesToAway
asm("fadd.d %0, %1, %2, rup" : "=f"(result_up) : "f"(x), "f"(y)); // roundTowardPositive
asm("fadd.d %0, %1, %2, rdn" : "=f"(result_down) : "f"(x), "f"(y)); // roundTowardNegative
asm("fadd.d %0, %1, %2, rtz" : "=f"(result_zero) : "f"(x), "f"(y)); // roundTowardZero
I'm not going to implement this right now, because I don't have a working GHC for RISC-V.
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