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cvm: consistency in cpuid features and xsave support #2691
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c842b3d
revoke avx features if xsave is not enabled for them
sluck-msft 1f51498
move some intel-specific bits into the tdx section
sluck-msft ced7e54
don't filter out vnni_int16
sluck-msft d641186
add a unit test
sluck-msft f1a01d3
add logging
sluck-msft e51dd31
update vnni_int16 as well
sluck-msft 1dcd2c5
fix unit tests
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -83,6 +83,25 @@ impl CpuidArchInitializer for TdxCpuidInitializer<'_> { | |
| .into(), | ||
| true, | ||
| )) | ||
| } else if subleaf == 1 { | ||
| Some(CpuidResultMask::new( | ||
| cpuid::ExtendedFeatureSubleaf1Eax::new() | ||
| .with_avx_vnni(true) | ||
| .with_avx512_bfloat16(true) | ||
| .with_fzlrep_movsb(true) | ||
| .with_fsrep_stosb(true) | ||
| .with_fsrep_cmpsb(true) | ||
| .with_avx_ifma(true) | ||
| .into(), | ||
| 0, | ||
| 0, | ||
| cpuid::ExtendedFeatureSubleaf1Edx::new() | ||
| .with_avx_vnni_int8(true) | ||
| .with_avx_vnni_int16(true) | ||
|
Contributor
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. @chris-oo avx_vnni_int16 is the new bit being filtered in. Lmk if you prefer we don't make this change.
Contributor
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. (I still haven't tested yet that TDX boots) |
||
| .with_avx_ne_convert(true) | ||
| .into(), | ||
| true, | ||
| )) | ||
| } else { | ||
| None | ||
| } | ||
|
|
@@ -347,4 +366,79 @@ impl CpuidArchInitializer for TdxCpuidInitializer<'_> { | |
|
|
||
| [l0, l1, l2, l3, l4] | ||
| } | ||
|
|
||
| fn update_xsave_dependencies(&self, xsave_support: u64, results: &mut CpuidResults) { | ||
| let mut clear_extended_features0_edx = cpuid::ExtendedFeatureSubleaf0Edx::new(); | ||
| let mut clear_extended_features1_eax = cpuid::ExtendedFeatureSubleaf1Eax::new(); | ||
| let mut clear_extended_features1_edx = cpuid::ExtendedFeatureSubleaf1Edx::new(); | ||
|
|
||
| let mut disable_avx_512 = false; | ||
|
|
||
| if (xsave_support & xsave::XFEATURE_YMM != xsave::XFEATURE_YMM) | ||
| || (xsave_support & xsave::XFEATURE_SSE != xsave::XFEATURE_SSE) | ||
| { | ||
| clear_extended_features1_eax.set_avx_vnni(true); | ||
| clear_extended_features1_eax.set_avx_ifma(true); | ||
|
|
||
| clear_extended_features1_edx.set_avx_vnni_int8(true); | ||
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|
||
| clear_extended_features1_edx.set_avx_vnni_int16(true); | ||
| clear_extended_features1_edx.set_avx_ne_convert(true); | ||
|
|
||
| disable_avx_512 = true; | ||
| } | ||
|
|
||
| if disable_avx_512 || (xsave_support & xsave::XFEATURE_AVX512 != xsave::XFEATURE_AVX512) { | ||
| clear_extended_features1_eax.set_avx512_bfloat16(true); | ||
| } | ||
|
|
||
| if xsave_support & xsave::XFEATURE_AMX != xsave::XFEATURE_AMX { | ||
| clear_extended_features0_edx.set_amx_tile(true); | ||
| clear_extended_features0_edx.set_amx_int8(true); | ||
| clear_extended_features0_edx.set_amx_bf16(true); | ||
| } | ||
|
|
||
| let extended_features0_entry = results | ||
| .leaf_result_mut_ref(CpuidFunction::ExtendedFeatures, Some(0)) | ||
| .expect("validated this leaf exists"); | ||
|
|
||
| let clearing_edx = cpuid::ExtendedFeatureSubleaf0Edx::from( | ||
| extended_features0_entry.edx & clear_extended_features0_edx.into_bits(), | ||
| ); | ||
|
|
||
| if clearing_edx.into_bits() != 0 { | ||
| tracing::warn!( | ||
| CVM_ALLOWED, | ||
| ?clear_extended_features0_edx, | ||
| ?xsave_support, | ||
| "Disabling features in cpuid leaf 7.0 due to missing xsave support.", | ||
| ); | ||
| } | ||
|
|
||
| extended_features0_entry.edx &= !clear_extended_features0_edx.into_bits(); | ||
|
|
||
| let extended_features1_entry = results | ||
| .leaf_result_mut_ref(CpuidFunction::ExtendedFeatures, Some(1)) | ||
| .expect("validated this leaf exists"); | ||
|
|
||
| let clearing_eax = cpuid::ExtendedFeatureSubleaf1Eax::from( | ||
| extended_features1_entry.eax & u32::from(clear_extended_features1_eax), | ||
| ); | ||
|
|
||
| let clearing_edx = cpuid::ExtendedFeatureSubleaf1Edx::from( | ||
| extended_features1_entry.edx & u32::from(clear_extended_features1_edx), | ||
| ); | ||
|
|
||
| if (clearing_eax.into_bits() != 0) || (clearing_edx.into_bits() != 0) { | ||
| tracing::warn!( | ||
| CVM_ALLOWED, | ||
| ?clear_extended_features1_eax, | ||
| ?clear_extended_features1_edx, | ||
| ?xsave_support, | ||
| "Disabling features in cpuid leaf 7.1 due to missing xsave support.", | ||
| ); | ||
| } | ||
|
|
||
| extended_features1_entry.eax &= !clear_extended_features1_eax.into_bits(); | ||
| extended_features1_entry.edx &= !clear_extended_features1_edx.into_bits(); | ||
| } | ||
| } | ||
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Do we still want to filter these out on AMD and ARM? #Closed
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ah I see you moved this to TDX specifically