[Build] FP4 QMoE in Windows - #32163
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Pull request overview
Enables FP4 QMoE builds on Windows/MSVC by isolating native SM120 CUDA sources and applying a targeted host-alignment workaround.
Changes:
- Splits FP4 QMoE sources into dedicated object libraries.
- Uses virtual SM120 PTX for general MSVC LLM sources.
- Enables SM120 grouped-TMA kernels with
/Zc:__cplusplus-.
Reviewed changes
Copilot reviewed 5 out of 5 changed files in this pull request and generated 1 comment.
Show a summary per file
| File | Description |
|---|---|
cmake/CMakeLists.txt |
Removes the MSVC FP4 QMoE build prohibition. |
cmake/onnxruntime_cuda_source_filters.cmake |
Adds FP4 source extraction and architecture replacement. |
cmake/onnxruntime_providers_cuda.cmake |
Configures dedicated CUDA provider object targets. |
cmake/onnxruntime_providers_cuda_plugin.cmake |
Mirrors the configuration for the plugin provider. |
docs/contrib_ops/cuda/moe_qmoe.md |
Documents Windows SM120 build behavior. |
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Co-authored-by: tianleiwu <30328909+tianleiwu@users.noreply.github.com>
Baiju Meswani (baijumeswani)
approved these changes
Aug 19, 2026
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Description
Enable FP4 QMoE for Blackwell SM120 in Windows CUDA builds. Previously, MSVC builds rejected this configuration because compiling the full LLM CUDA source set for native SM120 exposed
tcgen05compilation failures.Changes
onnxruntime_providers_cuda_llm_fp4onnxruntime_providers_cuda_plugin_llm_fp4sm_120a(120-real) soexpandInputRowsKernelcan usecvt.e2m1x2.compute_120PTX (120-virtual) on MSVC, avoidingtcgen05failures in unrelated translation units./Zc:__cplusplus-only to the host compilation of the SM120 TMA object target. This avoids MSVCC2719errors in generated host stubs for by-value, 128-byte-alignedCUtensorMapparameters while preserving C++20 for CUDA device compilation.Validation
sm_120awith MSVC and CUDA 13.