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codal_port/ticks_cpu: Check CoreDebug DEMCR trace enable bit. #199

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merged 1 commit into from
Apr 22, 2024

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microbit-carlos
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The DAPLink controlled reset button performs a target reset via SWD, and the CoreDebug trace enable bit seems to be cleared while the DWT->CTRL cycle count enable bit is not.

Fixes #179 (comment).

The DAPLink controlled reset button performs a target reset via
SWD, and the CoreDebug trace enable  bit seems to be cleared
while the DWT->CTRL cycle count enable bit is not.

#179 (comment)
@dpgeorge dpgeorge merged commit 90b9b7d into master Apr 22, 2024
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@dpgeorge dpgeorge deleted the ticks_cpu branch April 22, 2024 04:36
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Nice find! I tested this and it fixes the issue.

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Unexpected CPU cycle count with time.tick_cpu()
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