meiniKi
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cocktail Public
Forked from cocktail-collective/cocktailA model manager for Civitai
Python UpdatedJan 29, 2025 -
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esphome-sound-level-meter Public
Forked from stas-sl/esphome-sound-level-meterJupyter Notebook UpdatedJan 23, 2025 -
Paper2Go Public
Paper2Go converts documents to an AI-summarized audiobook.
Python MIT License UpdatedJan 17, 2025 -
Checkr Public
A minimalistic UI for grammar correction with self-hosted AI.
Python MIT License UpdatedJan 17, 2025 -
GameGrid64 Public
GameGrid64 is a 64x64 LED Matrix gaming console that was created as a weekend project.
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ttihp-FazyRV-ExoTiny Public template
Forked from TinyTapeout/ttihp-verilog-templateSystemVerilog Apache License 2.0 UpdatedOct 23, 2024 -
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nextpnr Public
Forked from YosysHQ/nextpnrnextpnr portable FPGA place and route tool
C++ ISC License UpdatedOct 9, 2024 -
corescore Public
Forked from olofk/corescoreCoreScore
Verilog Apache License 2.0 UpdatedSep 4, 2024 -
FazyRV Public
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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SimIO Public
SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.
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clash-ethernet Public
Forked from GiPHouse/qbaylogic-clash-based-macipudp-stack-spring24A fully configurable Ethernet core written in Clash.
Haskell Other UpdatedAug 20, 2024 -
OpenLane Public
Forked from The-OpenROAD-Project/OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Python Apache License 2.0 UpdatedMay 14, 2024 -
edalize Public
Forked from olofk/edalizeAn abstraction library for interfacing EDA tools
Python BSD 2-Clause "Simplified" License UpdatedApr 29, 2024 -
fusesoc Public
Forked from olofk/fusesocPackage manager and build abstraction tool for FPGA/ASIC development
Python BSD 2-Clause "Simplified" License UpdatedApr 29, 2024 -
sock.sv Public
Forked from witchard/sock.svA simple TCP socket library for system verilog. Using the system verilog DPI, allows the user to read / write lines from a TCP socket connection.
C MIT License UpdatedApr 17, 2024 -
JSON.sv Public
Forked from milestone12/JSON.svSystemVerilog package for reading, manipulating, and writing JSON-formatted data
SystemVerilog Other UpdatedApr 17, 2024 -
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litex Public
Forked from enjoy-digital/litexBuild your hardware, easily!
C Other UpdatedMar 6, 2024 -
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tt05-submission-template Public template
Forked from TinyTapeout/tt05-submission-templateSubmission template for Tiny Tapeout 05
Tcl Apache License 2.0 UpdatedSep 11, 2023 -
apicula Public
Forked from YosysHQ/apiculaProject Apicula 🐝: bitstream documentation for Gowin FPGAs
Verilog MIT License UpdatedMay 29, 2023 -
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RV32I_SC_Logisim Public
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
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tt03-another-piece-of-pi Public
Forked from TinyTapeout/tt03-submission-templateTiny Tapeout 03: Another Piece of Pi
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embench-iot Public
Forked from antmicro/embench-iotThe main Embench repository
C GNU General Public License v3.0 UpdatedJan 11, 2023