a workaround for LB=0

meiniKi · Oct 20, 2023 · bedcc28 · bedcc28
1 parent 9376f9d
commit bedcc28
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Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/rtl/serv_bufreg.v b/rtl/serv_bufreg.v
@@ -21,7 +21,8 @@ module qerv_bufreg #(
    //Data
    input wire [BITS_PER_CYCLE-1:0] i_rs1,
    input wire [BITS_PER_CYCLE-1:0] i_imm,
-   input wire [LB-1:0]  i_shift_counter_lsb,
+   // i_shift_counter_lsb[LB] must be zero to support the case LB=0
+   input wire [LB:0]  i_shift_counter_lsb,
    output wire [BITS_PER_CYCLE-1:0] o_q,
    //External
    output wire [31:0] o_dbus_adr,
@@ -38,8 +39,8 @@ module qerv_bufreg #(
    reg [1:0]            lsb;
    wire [LB:0]      shift_counter_rev = BITS_PER_CYCLE - i_shift_counter_lsb;
 
-   wire [LB-1:0] shift_amount = i_shift_op ? (
-       i_right_shift_op ? (i_shift_counter_lsb == 2'b00 ? 2'b00 : (shift_counter_rev[LB-1:0])) : i_shift_counter_lsb
+   wire [LB:0] shift_amount = i_shift_op ? (
+       i_right_shift_op ? (i_shift_counter_lsb == 00 ? 0 : (shift_counter_rev[LB:0])) : i_shift_counter_lsb
    ) : 0;
 
    wire 	      clr_lsb = i_cnt0 & i_clr_lsb;

diff --git a/rtl/serv_top.v b/rtl/serv_top.v
@@ -392,7 +392,7 @@ module qerv_top
       //Data
       .i_rs1    (rs1),
       .i_imm    (imm),
-      .i_shift_counter_lsb(shift_counter_lsb[1:0]),
+      .i_shift_counter_lsb({1'b0, shift_counter_lsb[1:0]}),
       .o_q      (bufreg_q),
       //External
       .o_dbus_adr (o_dbus_adr),