Encode and decode Eurobalise contents as described in ETCS subset 36

Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development

Linsn RV901T HUB75 LED "Receiver Card" Reverse Engineering

Collection of procedures and optimizations to Padavan Firmware.

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Build your hardware, easily!

Xilinx PCIe to MIG DDR4 example designs and custom part data files

adjust the CRC32/32c checksum of data to any desired value

Xlinix Kintex 7 based PCIE development board

bpfjit extracted from NetBSD

cBPF to C or eBPF compiler

Betrusted main SoC design

U8glib library for monochrome displays, version 2

IP submodules, formatted for easier CI integration

TangNano-20K-example

An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Notes on the Red Pitaya Open Source Instrument

The repo maintain PlutoSDR+

hBPF = eBPF in hardware

Verilog I2C interface for FPGA implementation

ECP5 breakout board in a feather physical format

Small footprint and configurable DRAM core

Verilog Ethernet components for FPGA implementation

Vitis Libraries