zephyr: stm32n6 support #2348
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zephyr: stm32n6 support #2348
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erwango
requested review from
nordicjm,
de-nordic and
davidvincze
as code owners
nordicjm
requested changes
Jun 20, 2025
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@nordicjm PTAL |
nordicjm
approved these changes
Jun 23, 2025
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rebase on |
With CONFIG_STM32_MEMMAP flag get NOR flash 32 bytes header Read the NOR flash to get header of the image. The FLASH_DEVICE is now the external NOR defined by the board device tree to be the first qspi/ospi/xspi instance (not necessarily zephyr, flash-controller) Signed-off-by: Francois Ramu <francois.ramu@st.com> Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
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Hold-On, I'll push a different approach of the mcuboot target. |
Add mcuboot configuration for stm32n6570_dk. Run in L&R mode and launch application in DIRECT XIP. Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
On STM32N6, MCUBoot is loaded by the BootROM to axisram2 and, when running in RAMLOAD configuration, application image is loaded in axisram1. To support this, define MULTIPLE_EXECUTABLE_RAM_REGIONS and implement boot_get_image_exec_ram_info() which provides the right executable address and size based on axisram1 node definition. Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
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Updated following new variant addition in zephyrproject-rtos/zephyr#91941 |
de-nordic
reviewed
Jun 25, 2025
Comment on lines
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| #ifdef CONFIG_SOC_SERIES_STM32N6X | ||
| #define MULTIPLE_EXECUTABLE_RAM_REGIONS | ||
| #endif |
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I do not think we should have SOC specific Kconfigs here. We rather should add some Kconfig to manipulate MULTIPLE_EXECUTABLE_RAM_REGIONS directly and then have it selected in soc/board prj.conf.
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@de-nordic So, where this new Kconfig should be defined, zephyr ?
de-nordic
approved these changes
Jun 25, 2025
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Generally looks OK, comment https://github.com/mcu-tools/mcuboot/pull/2348/files#r2166224346 is assumed to be addressed later.
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Cherry-pick of #2323 adding STM32N6 support with XIP and RAMLOAD support