Derive SAI blocks for 1176 from SAI1

All SAI instances can derive their register blocks from SAI1. While not
every instance has multiple tx/rx lines and fifos the register layout
can be reused for all SAI instances. The mcux sdk actually does this
by casting the instance address to I2S_Type* which is a common struct
with a common register layout.

CHANGELOG.md

@@ -2,6 +2,11 @@
 
 ## [Unreleased]
 
+**BREAKING** In the 1176 API, there is only one SAI module. All SAI instances,
+including those that only have a single channel, now appear to support multiple
+channels. The user is responsible for making sure their SAI instance can
+truly support multiple channels.
+
 **BREAKING** The `flexio1` module is now called `flexio` for the 1010,
 1015, and 1020 families.
 

devices/imxrt1176_cm4.yaml

@@ -108,6 +108,9 @@ _derive:
   GPIO11: GPIO2
   GPIO12: GPIO2
   GPIO13: GPIO2
+  SAI2: SAI1
+  SAI3: SAI1
+  SAI4: SAI1
 
 # All of the directives below this comment are removing or simplifying
 # duplicated enumeratedValue fields in select register fields. These prevent

devices/imxrt1176_cm7.yaml

@@ -46,6 +46,12 @@ _add:
       size: 0x14
       usage: registers
 
+# SAI[2-4] should reuse the register block from SAI1
+_derive:
+  SAI2: SAI1
+  SAI3: SAI1
+  SAI4: SAI1
+
 # All of the directives below this comment are removing or simplifying
 # duplicated enumeratedValue fields in select register fields. These prevent
 # compilation due to duplicate symbols.

src/blocks/imxrt1176_cm4/sai.rs

@@ -18,11 +18,11 @@ pub struct RegisterBlock {
     #[doc = "Transmit Configuration 5"]
     pub TCR5: crate::RWRegister<u32>,
     #[doc = "Transmit Data"]
-    pub TDR0: crate::RWRegister<u32>,
-    _reserved0: [u8; 0x1c],
+    pub TDR: [crate::RWRegister<u32>; 4usize],
+    _reserved0: [u8; 0x10],
     #[doc = "Transmit FIFO"]
-    pub TFR0: crate::RORegister<u32>,
-    _reserved1: [u8; 0x1c],
+    pub TFR: [crate::RORegister<u32>; 4usize],
+    _reserved1: [u8; 0x10],
     #[doc = "Transmit Mask"]
     pub TMR: crate::RWRegister<u32>,
     _reserved2: [u8; 0x24],
@@ -39,11 +39,11 @@ pub struct RegisterBlock {
     #[doc = "Receive Configuration 5"]
     pub RCR5: crate::RWRegister<u32>,
     #[doc = "Receive Data"]
-    pub RDR0: crate::RORegister<u32>,
-    _reserved3: [u8; 0x1c],
+    pub RDR: [crate::RORegister<u32>; 4usize],
+    _reserved3: [u8; 0x10],
     #[doc = "Receive FIFO"]
-    pub RFR0: crate::RORegister<u32>,
-    _reserved4: [u8; 0x1c],
+    pub RFR: [crate::RORegister<u32>; 4usize],
+    _reserved4: [u8; 0x10],
     #[doc = "Receive Mask"]
     pub RMR: crate::RWRegister<u32>,
 }
@@ -471,7 +471,15 @@ pub mod TCR3 {
     #[doc = "Transmit Channel Enable"]
     pub mod TCE {
         pub const offset: u32 = 16;
-        pub const mask: u32 = 0x01 << offset;
+        pub const mask: u32 = 0x0f << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {}
+    }
+    #[doc = "Channel FIFO Reset"]
+    pub mod CFR {
+        pub const offset: u32 = 24;
+        pub const mask: u32 = 0x0f << offset;
         pub mod R {}
         pub mod W {}
         pub mod RW {}
@@ -588,6 +596,23 @@ pub mod TCR4 {
             pub const FPACK_3: u32 = 0x03;
         }
     }
+    #[doc = "FIFO Combine Mode"]
+    pub mod FCOMB {
+        pub const offset: u32 = 26;
+        pub const mask: u32 = 0x03 << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {
+            #[doc = "FIFO combine mode disabled."]
+            pub const FCOMB_0: u32 = 0;
+            #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."]
+            pub const FCOMB_1: u32 = 0x01;
+            #[doc = "FIFO combine mode enabled on FIFO writes (by software)."]
+            pub const FCOMB_2: u32 = 0x02;
+            #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."]
+            pub const FCOMB_3: u32 = 0x03;
+        }
+    }
     #[doc = "FIFO Continue on Error"]
     pub mod FCONT {
         pub const offset: u32 = 28;
@@ -630,7 +655,7 @@ pub mod TCR5 {
     }
 }
 #[doc = "Transmit Data"]
-pub mod TDR0 {
+pub mod TDR {
     #[doc = "Transmit Data Register"]
     pub mod TDR {
         pub const offset: u32 = 0;
@@ -641,7 +666,7 @@ pub mod TDR0 {
     }
 }
 #[doc = "Transmit FIFO"]
-pub mod TFR0 {
+pub mod TFR {
     #[doc = "Read FIFO Pointer"]
     pub mod RFP {
         pub const offset: u32 = 0;
@@ -658,6 +683,19 @@ pub mod TFR0 {
         pub mod W {}
         pub mod RW {}
     }
+    #[doc = "Write Channel Pointer"]
+    pub mod WCP {
+        pub const offset: u32 = 31;
+        pub const mask: u32 = 0x01 << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {
+            #[doc = "No effect."]
+            pub const WCP_0: u32 = 0;
+            #[doc = "FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write."]
+            pub const WCP_1: u32 = 0x01;
+        }
+    }
 }
 #[doc = "Transmit Mask"]
 pub mod TMR {
@@ -1042,7 +1080,15 @@ pub mod RCR3 {
     #[doc = "Receive Channel Enable"]
     pub mod RCE {
         pub const offset: u32 = 16;
-        pub const mask: u32 = 0x01 << offset;
+        pub const mask: u32 = 0x0f << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {}
+    }
+    #[doc = "Channel FIFO Reset"]
+    pub mod CFR {
+        pub const offset: u32 = 24;
+        pub const mask: u32 = 0x0f << offset;
         pub mod R {}
         pub mod W {}
         pub mod RW {}
@@ -1146,6 +1192,23 @@ pub mod RCR4 {
             pub const FPACK_3: u32 = 0x03;
         }
     }
+    #[doc = "FIFO Combine Mode"]
+    pub mod FCOMB {
+        pub const offset: u32 = 26;
+        pub const mask: u32 = 0x03 << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {
+            #[doc = "FIFO combine mode disabled."]
+            pub const FCOMB_0: u32 = 0;
+            #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers)."]
+            pub const FCOMB_1: u32 = 0x01;
+            #[doc = "FIFO combine mode enabled on FIFO reads (by software)."]
+            pub const FCOMB_2: u32 = 0x02;
+            #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software)."]
+            pub const FCOMB_3: u32 = 0x03;
+        }
+    }
     #[doc = "FIFO Continue on Error"]
     pub mod FCONT {
         pub const offset: u32 = 28;
@@ -1188,7 +1251,7 @@ pub mod RCR5 {
     }
 }
 #[doc = "Receive Data"]
-pub mod RDR0 {
+pub mod RDR {
     #[doc = "Receive Data Register"]
     pub mod RDR {
         pub const offset: u32 = 0;
@@ -1199,7 +1262,7 @@ pub mod RDR0 {
     }
 }
 #[doc = "Receive FIFO"]
-pub mod RFR0 {
+pub mod RFR {
     #[doc = "Read FIFO Pointer"]
     pub mod RFP {
         pub const offset: u32 = 0;
@@ -1208,6 +1271,19 @@ pub mod RFR0 {
         pub mod W {}
         pub mod RW {}
     }
+    #[doc = "Receive Channel Pointer"]
+    pub mod RCP {
+        pub const offset: u32 = 15;
+        pub const mask: u32 = 0x01 << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {
+            #[doc = "No effect."]
+            pub const RCP_0: u32 = 0;
+            #[doc = "FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read."]
+            pub const RCP_1: u32 = 0x01;
+        }
+    }
     #[doc = "Write FIFO Pointer"]
     pub mod WFP {
         pub const offset: u32 = 16;