First Commit. Report Added.

.gitignore

@@ -0,0 +1,5 @@
+*.aux
+*.log
+*.pdf
+*.jpg
+/images

abstract.tex

@@ -0,0 +1,23 @@
+\thispagestyle{plain}
+
+\begin{center}
+	\vspace{1cm}
+
+	\bigsize{\textbf{Development of Verification Environment for SHA-3 Core using UVM}}
+
+	\vspace{1.5cm}
+
+			\normalsize
+			By\\
+			\textbf{Mayur Navinchandra Kubavat}\\
+			\textbf{(131060752013)} \\
+			Guided By\\
+			\textbf{Mr.Ashish Prabhu}\\
+			\textbf{Sr. Verification Engineer, LSI India R\&D}
+
+	\bigsize\textbf\textit\underline{ABSTRACT}
+\end{center}
+
+As CMOS technology advances, complexity of ICs also increases. Moore’s law states that number of transistor in ICs doubles approximately every two years. Verifying working of these complex digital systems has become more important now, because any small deviation from specification in high density chips can lead to system failure and complete re-spin of the design cycle. Which then leads to increased cost and delay in time-to-market. Therefore SystemVerilog HVL was developed to create testbench for large digital design. SystemVerilog supports concepts of OOPs and provide higher level of abstraction in our testbench. To support reusability of verification components UVM is developed later which is derived from OVM and eRM. \par
+
+This dissertation work is induced from necessity of development of UVM based verification environment. Proposed work in this thesis describes flow from specification extraction to development of verification environment and implements UVM based reusable verification environment. \par

abstract2.tex

@@ -0,0 +1,3 @@
+\thispagestyle{plain}
+
+Expected result from this dissertation work includes, developing of UVM component for verification environment, integrating design under test with developed environment, creating test cases, complete code coverage and detailed documentation about them all. We also try to achieve higher functional coverage report in our verification environment. Use of scripting is made to execute commands in batch mode. The verification environment is reused between low and high-throughput cores. This dissertation work on development of UVM based verification environment will try to bridge gap between Academia and Indutry practices.

acknowledge.tex

@@ -0,0 +1,16 @@
+\thispagestyle{plain}
+
+\begin{center}
+	\midsize\textbf{\underline {ACKNOWLEDGMENT}}
+	\addcontentsline{toc}{chapter}{Acknowledgment}
+\end{center}
+
+I would like to express my deepest appreciation to all those who provided me the possibility to complete this report. A special gratitude I give to our guide \textbf{Mr. Ashish Prabhu}, Sr. Verification Engineer, LSI R\&D India, Pune, whose contribution in stimulating suggestions and encouragement helped me to coordinate my report writing.
+
+Credits also go to my friends and senior students, including \textbf{Pankaj Chavda} for his valuable suggestion and support time and again.
+
+And I thank \textbf{Gujarat Technological University, Ahmedabad} and \textbf{CDAC ACTS, Pune} for providing IEEE Xplore subscription.
+
+\vspace{4cm}
+
+	\hfill \hfill \textbf{Mayur Kubavat} (131060752013)

acknowledge2.tex

@@ -0,0 +1,3 @@
+\thispagestyle{plain}
+
+Expected result from this dissertation work includes, developing of UVM component for verification environment, integrating design under test with developed environment, creating test cases, development of functional model, complete code coverage and detailed documentation about them all. We also try to achieve higher functional coverage report and foreign language integration in our verification environment. Scripting can be used to execute commands in batch mode. The verification environment can also be reused between low and high-throughput cores as well. Also some design concept can be studied to find new ways of optimizing FPGA implementations.

appendix.tex

@@ -0,0 +1,4 @@
+\begin{appendices}
+\chapter{Some Appendix}
+The contents...
+\end{appendices}

appendixa.tex

@@ -0,0 +1,25 @@
+\begin{appendices}
+\chapter{List of Abbreviations}
+\NumTabs{6}
+
+IEEE		\tab{Institute of Electrical and Electronics Engineers} \\
+ASIC		\tab{Application Specific Integrated Circuit} \\
+EDA			\tab{Electronic Design Automation} \\
+RTL			\tab{Register Transfer Level} \\
+HDL			\tab{Hardware Description Language} \\
+FPDA		\tab{Field Programmable Gate Array} \\
+DSP			\tab{Digital Signal Processing} \\
+FIFO		\tab{First In First Out} \\
+DUT-TB		\tab{Design Under Test - Testbench} \\
+VC 			\tab{Verification Component} \\
+VIP 		\tab{Verification Intellectual Property (IP)} \\
+UVM 		\tab{Universal Verification Methodology} \\
+OVM 		\tab{Open Verification Methodology} \\
+eRM 		\tab{e Reuse Methodology} \\
+VMM 		\tab{Verification Methodology Manual} \\
+AVM 		\tab{Advanced Verification Methodology} \\
+NIST 		\tab{National Institute of Standards and Technology} \\
+FIPS-PUB 	\tab{Federal Information Processing Standards  Publication} \\
+SHA 		\tab{Secure Hash Algorithm} \\
+AES 		\tab{Advanced Encryption Standard} \\
+RSA 		\tab{Ron Rivest, Adi Shamir and Leonard Adleman}

appendixb.tex

@@ -0,0 +1,83 @@
+\chapter{Package File: sha3\_pkg.svh}
+
+\begin{verbatim}
+package sha3_pkg;
+
+// Include Package Items and Macros
+import uvm_pkg::*;
+`include "uvm_macros.svh"
+
+// Define Sequencer, Include Sequence Items   
+`include "sequence_item.svh"
+typedef uvm_sequencer#(sequence_item) sequencer;
+
+// Sequences
+`include "sequences/base_sequence.svh"
+`include "sequences/reset_seq.svh"
+`include "sequences/msg_seq.svh"
+`include "sequences/empty_msg_seq.svh"
+`include "sequences/long_msg_seq.svh"
+`include "sequences/tr1_seq.svh"
+`include "sequences/tr2_seq.svh"
+`include "sequences/tr3_seq.svh"
+`include "sequences/tr4_seq.svh"
+
+// UVM Components
+`include "sha3_driver.svh"
+`include "sha3_monitor.svh"
+`include "sha3_agent_config.svh"
+`include "sha3_agent.svh"
+`include "sha3_scoreboard.svh"
+`include "sha3_env.svh"
+
+// Base Test and Extended Tests 
+`include "test/sha3_base_test.svh"
+`include "test/tr1_test.svh"
+`include "test/tr2_test.svh"
+`include "test/tr3_test.svh"
+`include "test/tr4_test.svh"
+
+endpackage: sha3_pkg
+
+\end{verbatim}
+
+\newpage
+\section{File System Hierarchy}
+% To print plaintext
+\begin{verbatim}
+sha3_uvm
+|__ main
+|    |__ high_throughput_core
+|    |__ low_throughput_core
+|    |__ testbench
+|          |__ sequences
+|          |      |__ msg_seq.svh
+|          |      |__ reset_seq.svh
+|          |      |__ rndmsg_seq.svh
+|          |      |__ empty_seq.svh
+|          |      |__ tr1_seq.svh
+|          |      |__ tr2_seq.svh
+|          |      |__ tr3_seq.svh
+|          |      |__ tr4_seq.svh
+|          |__ test
+|          |      |__ sha3_base_test.svh
+|          |      |__ tr1_test.svh
+|          |      |__ tr2_test.svh
+|          |      |__ tr3_test.svh
+|          |      |__ tr4_test.svh
+|          |__ sequence_item.svh
+|          |__ sha3_agent.svh
+|          |__ sha3_driver.svh
+|          |__ sha3_env.svh
+|          |__ sha3_monitor.svh
+|          |__ sha3_scoreboard.svh
+|__ dut_htc.f
+|__ dut_ltc.f
+|__ interface_htc.sv
+|__ interface_ltc.sv
+|__ run.do
+|__ sha3_pkg.svh
+|__ tb.f
+|__ top.sv
+|__testcases.xlsx
+\end{verbatim}

appendixc.tex

@@ -0,0 +1,3 @@
+\addcontentsline{toc}{chapter}{Paper}
+\includepdf[pages={1-5}]{1432358802.pdf}
+\includepdf[pages={1}]{eCertificate.pdf}

appendixd.tex

@@ -0,0 +1,30 @@
+\chapter{}
+\addcontentsline{toc}{chapter}{Review Card Compliance}
+%Image
+\includepdf{01.jpg}
+
+%Image
+\includepdf{02.jpg}
+
+%Image
+\includepdf{03.jpg}
+
+%Image
+\includepdf{04.jpg}
+
+%Image
+\includepdf{05.jpg}
+
+\begin{table}[ht]
+\begin{tabulary}{1.0\textwidth}{|C|L|L|}
+\hline
+	No. & Comments Given By External Review Panel & Mdification done based on Comments\\
+\hline
+	1 & \nextitem Instead of generalized verification plan, a detailed verification plan for your project should be written.\nextitem Literature survey on more IEEE papers should be done. & Came up with specific testplan and working on it.\\
+\hline
+	2 & More testcases for specification is required & Came up with more test scenarios and different combinations and started working on coding and implementation of them.\\
+\hline
+	3 & \nextitem Publish one paper in reputed journal. \nextitem Verification concept extend, upto functional verification \nextitem Implement on Xilinx FPGA for throughput and power considerations. & Paper has been published in a reputed journal on May 15, 2015 issue. \nextitem Verification concept has been extended for functional coverage introduction in DUT. \nextitem As work is verification with SV UVM, design \& implementation not considered and are out of the scope of the theme.\\
+\hline
+\end{tabulary}
+\end{table}

appendixe.tex

@@ -0,0 +1,5 @@
+\addcontentsline{toc}{chapter}{Progress Report}
+
+\includepdf[pages={1-4}]{Report4Page.pdf}
+
+\end{appendices}

approvalcerti.tex

@@ -0,0 +1,22 @@
+\thispagestyle{plain}
+
+\thiswatermark{\centering \put(0,-575){\includegraphics[scale=0.4]{gtu-hd-rgb.png}} }
+
+\begin{center}
+	\midsize\textbf{\underline {THESIS APPROVAL CERTIFICATE}}
+	\addcontentsline{toc}{chapter}{Thesis Approval Certificate}
+\end{center}
+
+This is to certify that research work embodied in this thesis entitled \textbf{``Development of Verification Environment for SHA-3 Core using UVM"} carried out by \textbf{Mr. Mayur Navinchandra Kubavat} (Enrollment No. \textbf{131060752013}) at \textbf{Gujarat Technological University PG School (106), Ahmedabad} is approved for the degree of Master of Engineering with specialization of \textbf{(Electronics \& Communication Engineering) in VLSI \& Embedded Systems Design} by Gujarat Technological University.
+
+    \vspace {0.5cm}
+
+    \textbf{Date: June 2015} \\
+    \textbf{Place: Ahmedabad}
+
+    \vspace {1.0cm}
+
+	\textbf{Examiners Sign and Name:}
+	\vspace{1.0cm}
+
+	.........................................................				.........................................................

cdac.tex

@@ -0,0 +1,3 @@
+\addcontentsline{toc}{chapter}{CDAC Certificate}
+%Image
+\includepdf{CDAC.jpg}

certificate.tex

@@ -0,0 +1,31 @@
+\thispagestyle{plain}
+
+\begin{center}
+	\midsize\textbf{\underline {CERTIFICATE}}
+	\addcontentsline{toc}{chapter}{Certificate}
+\end{center}
+
+This is to certify that research work embodied in this Thesis entitled \textbf{"Development of Verification Environment for SHA-3 Core using UVM"} was carried out by \textbf{Mr. Mayur Navinchandra Kubava (131060752011) at Gujarat Technological University PG School (106), Ahmedabad} for partial fulfillment of Master of Engineering degree, \textbf{(Electronics \& Communication Engineering) in VLSI \& Embedded Systems Design}, to be awarded by Gujarat Technological University. This research work has been carried out under my supervision and is to my satisfaction.
+
+    \vspace {1cm}
+
+    \textbf{Date: June 2015} \\
+    \textbf{Place: Ahmedabad}
+
+    \vspace{2cm}
+
+    \begin{tabular}{c m{4cm} c}
+    	\textbf{Signature of Guide} & & \textbf{Signature and Name} \\
+    	& & \textbf{of Principle} \\
+    \end{tabular}
+
+    \vspace{2.5cm}
+
+    \begin{center}
+
+	    	\textbf{Principal}\\
+	    	\vspace{2.5cm}
+	    	\textbf{Seal of Institute} 
+	\end{center}
+
+\thiswatermark{\centering \put(0,-575){\includegraphics[scale=0.4]{gtu-hd-rgb.png}} }

certificate2.tex

@@ -0,0 +1,35 @@
+\thispagestyle{plain}
+
+\thiswatermark{\centering \put(0,-575){\includegraphics[scale=0.4]{gtu-hd-rgb.png}} }
+
+
+\begin{center}
+	\midsize
+	\textbf{\underline {COMPLIANCE CERTIFICATE}}
+	\addcontentsline{toc}{chapter}{Compliance Certificate}
+\end{center}
+
+This is to certify that research work embodied in this thesis entitled \textbf{``Development of Verification Environment for SHA-3 Core using UVM"} was carried out by \textbf{Mr. Mayur Navinchandra Kubavat} (Enrollment No. \textbf{131060752013}) at \textbf{Gujarat Technological University PG School (106), Ahmedabad} for partial fulfillment of Master of Engineering degree, \textbf{(Electronics \& Communication Engineering) in VLSI \& Embedded Systems Design}, to be awarded by Gujarat Technological University. He has complied with the comments given by the Dissertation Phase-I as well as Mid Semester Thesis Reviewer to my satisfaction.
+
+   \begin{tabular}{c m{4cm} c}
+   	\textbf{Signature of Student:} & &\textbf{Signature of Guide:} \\
+   	\textbf{Kubavat Mayur N.} & &\textbf{Mr. Ashish Prabhu}
+   \end{tabular}
+
+\thispagestyle{plain}
+\vspace{0.5cm}	
+
+\begin{center}
+	\midsize
+	\textbf{\underline {PAPER PUBLICATION CERTIFICATE}}
+\end{center}
+
+This is to certify that research work embodied in this thesis entitled \textbf{``Development of Verification Environment for SHA-3 Core using UVM"} carried out by \textbf{Mr. Mayur Navinchandra Kubavat} (Enrollment No. \textbf{131060752013}) at \textbf{Gujarat Technological University PG School (106), Ahmedabad} for partial fulfillment of Master of Engineering degree, \textbf{(Electronics \& Communication Engineering) in VLSI \& Embedded Systems Design}, to be awarded by Gujarat Technological University, has published article entitled \textbf{``Development of UVM based Reusable Verification Environment for SHA-3 Cryptographic Core"} for publication by the \textbf {IJRITCC, during Volume 3 Issue 5 on 15 May 2015.}
+
+    \textbf{Date: June 2015} \\
+    \textbf{Place: Ahmedabad}
+
+   \begin{tabular}{c m{4cm} c}
+   	\textbf{Signature of Student:} & &\textbf{Signature of Guide:} \\
+   	\textbf{Kubavat Mayur N.} & &\textbf{Mr. Ashish Prabhu}
+   \end{tabular}

chap1.tex

@@ -0,0 +1,46 @@
+\chapter{Introduction}
+
+This report describes various facts used to select thesis statement “Development of verification environment for SHA-3 core using UVM” and follow up approach to realize development of solution for the problem stated. Here, verification environment for SHA-3 Cryptographic Core is proposed and developed using UVM methodology. Literature which is surveyed to come up for the thesis selection is outlined in Literature Survey section. SHA-3 is cryptographic hash function and used in many applications including data integrity, password matches, etc. Proposed verification uses concept of OOPs provided in SystemVerilog language with UVM industry standard methodology used in ASIC/SoC verification.
+
+\section{Problem Statement}
+
+This dissertation work is induced from need of development of UVM based verification environment for SHA-3 cryptographic core. Taking this need in consideration, dissertation work describes flow from specification extraction to development of verification environment.
+
+
+\section{Motivation}
+
+Following increasing logic complexity in digital ICs, verification requirements has also become complex. To address this issue SystemVerilog Hardware Verification Language (HVL) came into existence. SystemVerilog is comprehensive base language which supports OOPs and thus abstraction level in testbench. But, to practice reusability in our testbench environment, UVM methodology is developed later which has rich set of class library. \par
+
+SHA-1 is most widely known and used hash function in several applications and protocols. Many successful attacks have been noted on SHA-1 which led NIST to move to SHA-2 after 2010 because of the weakness in previous hash algorithm. Although no successful attacks have been noted on SHA-2, development of another option is necessary as future perspective. NIST has selected a new cryptographic hash algorithm which is referred to as the Secure Hash Algorithm 3 (SHA-3) and is intended to complement the SHA-2 hash algorithms currently specified in Federal Information Processing Standard (FIPS) 180-3, Secure Hash Standard. The selected algorithm is intended to be suitable for use by the U.S. government as well as the private sector and is available royalty-free worldwide\cite{fips202}. \par
+
+Combining above best practices, flow of development of verification environment for Keccak SHA-3 core using UVM is described in this report.
+
+\section{Scope}
+
+The thesis aims at applying hardware verification concept to the cryptographic core and check functional correctness of the core. Find out appropriate verification methodology and build verification environment according to it. Then integrating our developed environment with the design under test and verifying appropriate response in comparison to functional model while achieving complete code coverage. Scope of the dissertation work can also be extended to functional coverage and redefining hardware block by critical assessment of work done on Secure Hash Algorithms. Proposed environemt can be used to verify other cryptographic RTLs with minimun configuration changes exploiting reusability in UVM based environment.
+
+\section{Objectives}
+
+Work to be presented in this dissertation thesis aims at following standard verification flow used in industry to develop verification environment for the cryptographic core. \par
+
+Critically analyzing the relevant literature of Secure Hash Algorithm and Verification techniques with UVM is the first step. The work will follow standard practices to develop verification environment for verification methodology which is Universal Verification Methodology. \par
+
+One important aspect of hardware verification is code coverage, which will also be covered. \par
+
+Scope of this work can also be extended to generate functional coverage. Concept of reusability can also be explored. And area vs. throughput consideration can be analyzed and studied for hardware design improvements and FPGA implementation. \par
+
+\section{Research Methodology}
+
+First step in the dissertation flow is to understand Design under Test (DUT) specification. Following feature extraction from the design, this is specification of our Keccak SHA-3 core. Interpretation of design features is used to generate test scenarios under which selected RTL will be operating. \par
+
+It is then followed by testbench architecture development phase. This phase contains developing UVM testbench hierarchical components. Development and execution of environment is done on verification tool QuestaSim 10.0b by Mentor Graphics tool. Code coverage and functional coverage functionalities are also provided by Mentor Graphics Questa Advanced Simulator. \par
+
+File format like .sv .svh .do .f and etc for required verification environment are created using emacs editor under Linux Ubuntu 15.04. And documentation for creating thesis report is done on Gummi Latex Editor tool.\par
+
+Use of scripting language like Perl or TCL can also be studied to create Makefile or Do file and command line arguments to run tests and batch execution. \par
+
+Scope of this dissertation work if extended to design and implementation of SHA-3 Keccak on FPGA then other tools Xilinx ISE, Timing Tool Editor Etc can be used to create RTL code, linting and synthesizing the RTL and producing technology view of the RTL. And proposed verification environment can be applied to verify functionality of RTL using exhausted number of testcases provided.
+
+\section{Expected Outcome}
+
+Expected outcome from this dissertation work include, UVM based verification environment integrated with SHA-3 core, verification environment component will be created and mapped to UVM library. Complete code coverage will be achieved by applying randomly generated testcases. Checks for different test scenario will be done. And appropriate documentation of prescribed work will be done.